VHDL

I am trying get an idea from experienced enthusiasts. As a beginner should we learn both hdls or one, suggest pros and cons.

Hello all, I was recently let go from my position with a fortune 5 company after it was apparent the position was not for me and now I'm looking at other career options. I stumbled on FPGA as a possible choice. Programming in Python (which most employers want) give me anxiety for some reason but the hardware interfacing aspect of FPGA appeals to me. I only have experience with VHDL so far and I'm wondering what differences there are between each from veterans. Syntax is obvious but I'm not sure what else to expect or which one to focus on. Anyone able to provide clarity?

Hi. I just started a job as a firmware engineer and all the designs are written on VHDL, but testbenches are in system verilog. This is the first time I work with system verilog as I have only used VHDL in the past. I think it is a good opportunity to learn, but I am worried about how well things are mapped between both languages (particularly records in packages) and what problems should I expect. Also, is this mixing common? We are using VIVADO tools.

Having a hard time locating one.

Hey folks,

I'm diving into the world of VHDL after being working with Verilog, System Verilog and even UVM for almost 2 years. The transition has been... interesting, to say the least. Coming from a background where Verilog was my go-to for synthesis and simulation, VHDL feels like a whole new ball game.

Sure, I get that VHDL has its loyal followers, but as a beginner, I'm struggling to see the appeal. It feels overly verbose compared to Verilog. Plus, Verilog has served me well in my previous projects both using Vivado and Icarus Verilog, so why fix what isn't broken?

Before jumping to conclusions, I wanted to hear from the community: What advantages does VHDL offer over Verilog in terms of RTL design and synthesis? Are there any scenarios where VHDL reigns supreme, or is it just a matter of personal preference?

As an EE student in Germany, they use VHDL in several courses, but never actually teach how to use it. So basically I had to learn it through self-study, which is not always the easiest.

I am curious as to how you guys learned VHDL and possible resources, strategies, and everything else regarding your learning journey for VHDL

I've been teaching a third-year electrical engineering FPGA design course, initially using VHDL before switching to SystemVerilog. Despite my experience and students' solid foundation in digital design and C, this switch led to increased failures (coinciding with COVID and its impact on education). VHDL's strong typing seems beneficial for error prevention, whereas SystemVerilog's C-like syntax might falsely embolden students, accustomed to software programming, to overlook the hardware design mindset. Given SystemVerilog's industry relevance, especially in verification roles, I'm evaluating which language to focus on for aligning with practical, industry-relevant education. I use the Harris and Harris textbook. Seeking advice: Should I continue with SystemVerilog or return to VHDL?

I've done VHDL, Verilog, and SystemVerilog. I write pretty much exclusively SystemVerilog these days.

After a decade of experience, I've come to a soft conclusion that Verilog is so much better than VHDL. I've seen many comparisons where people show pros/cons and conclude that one is not better than the other. This certainly sounds like a mature conclusion. But in my actual experience, I just don't see how / when / why anyone would prefer VHDL. It just about always takes me much longer to write equivalent VHDL code.

Here are the most commonly cited advantages I hear for VHDL (along with my thoughts):

1. VHDL forces you to write more correct code. Sure, but at what cost? In my experience, once you get past beginner coder, you're not often going to be making simple typing / width errors. And they're easy to debug when you do. To me, it seems like a bad trade-off to force (sometime complicated) casting upon the user. I don't see how the benefits outweigh the overhead cost in the long-run. Just let me write what I want to write, dang it!

2. VHDL has library support. I actually see this as a disadvantage. In order to do simple things that Verilog and SystemVerilog has built into the language, you have to import libraries. And there's confusing overlapping implementations between libraries at times. And nobody ever seems to totally know what functions are in what libraries off the top of their heads. This slows down development. You want something like a simple 2D vector? You've gotta create a custom data type and import it everywhere. Furthermore, I find that libraries tend to get out of control over time, and end up bloating up projects.

3. VHDL is more easy to understand. No its not.

4. VHDL is deterministic. Referring to a simulation timestep. Okay, I'll give you this one. SystemVerilog has the cumbersome clocking block to deal with this issue.

Overall, I don't see how the benefits ever outweigh the cons. Maybe it has to do with how I think, or where I am in my career? Once I come up with a conceptual solution, I want to be able to translate that into HDL as fast and effortlessly as possible. But VHDL just seems to get in the way in this process, sucking the joy out of the design process.

Please, if you prefer VHDL, change my mind! I actually am open to other perspectives here!

Hi everyone,

I'm a first year EE student, and I just finished my first logic circuits class. I loved it so much that I asked my teacher for what I should do to learn more on the subject, and he told me wait for the next class. The next electronics class is in 2 years...

So I want to get into microelectronics, and I heard from seniors I should learn VHDL and I should goof around with FPGAs, but I have no idea where to start. Right now I know basic logic components, as well as sequential circuits. (I study in french I don't know the right english terms for it sorry)

Some labs I've done include a 4bit ALU with add/sub and 3 flags, and also my final big boss lab was an alarm system with a movement detector, so there was quite a bit of sequential logic there. Also, I have a macbook so I don't know if that's important for HDL.

If you know where I should start, please let me know! Thanks

Hi,

I’m the final year of BSc in Electrical and Computer engineering and I was wondering which HDL I’m gonna use when I finish my degree. In digital and VLSI design we mainly used VHDL, but do I need to learn Verilog if I know already VHDL? Of course, I am interested in digital and mixed signal system design, so do you think I will have any problems if I don’t know how to work in Verilog?

Currently I'm in the middle of a relatively large project and i feel like the way i organize my modules and generally my code is kinda subpar. Any general tips i should keep in my mind to keep my code from being more complex than it needs to be?

Hi guys,

Im a research assosciate right now and our Team(2 people), where only one is an electrical engineer is using VHDL. I personnally get to know Verilog due a course in university and wrote for my Masterthesis in VHDL. Due this time I experienced that the vast majority prefers Verilog over VHDL. I personally am free to use whatever I want. However a huge code base is generated as VHDL. So before swapping to Verilog I would like to know its benefits over VHDL. Can you help me in this regards?

Hello!

During my work, I have to write code for both SW and HW (FPGA).

While for SW, AI bots like ChatGPT (especially now with code interpreter) greatly reduced my load and create comprehensive, well structured code, for VHDL and Verilog, the situation is not too bright.

It takes me extensive instructions to direct AI to write a synthesizable code even for basic modules, and the mistakes he makes are very primitive, e.g. driving the signal from 2 different processes.

So my question is, why is it so different? Is it because the database for SW languages is so much bigger and more open-source, or because the models cannot comprehend the underlying rules for a synthesizable code (taking also timing into account, latency, etc..)?

Do you have any other LLM model which can make sufficiently good VHDL/Verilog code?

Thanks!

Question. Me and my roommates have been pondering this question for a while and can't find an answer. The process of writing code like C and Java is called programming, what is the process of writing VHDL and Verilog called? Are we just describing things?

EE undergrad here. I am very interested in getting into FPGA design and have been studying some on my own time. I was wondering if it would be better to learn Verilog or VHDL? Which is more widely used, which is easier to pick up, etc. are questions in my mind.

Hi guys, apparently Xilinx claims that they support VHDL-2008 since version .

At my work, I use Quartus which has really good support of VHDL-2008. In the past, I used Vivado and I remember that the synthesiser had better support than the simulator, which frustrated me a lot. Privately, I have Vivado installed but so far I never used it though. However, I'm designing something, which I want to test soon on a Xilinx board.

Well, if I check their pages for and .

They write:

AMD Vivado™ synthesis supports a synthesizable subset of the VHDL-2008 standard. The following section describes the supported subset and the procedures to use it.

The AMD Vivado™ simulator supports the subset of VHDL 2008 (IEEE 1076-2008). The complete list is given in Supported features of VHDL 2008 (IEEE1076-2008).

Sadly, they don't provide a list what are still missing though.
So my question is, do you know what kind of features they still miss?

Thank you & cheers

I would really appreciate your guys advice, my role at work (I’m early in my career) is a combination of embedded software and FPGA development, my boss thinks I am great with FPGA (he is wrong lol). But I am being tasked with a multiple months project in VHDL, fully emulating a chipset with about 100 page datasheet so medium complexity. The only problem, I have done only Verilog and System Verilog and need to learn VHDL fast! In Verilog/SV I’ve made a functioning out of order processor (w/ caches, branch prediction, superscalar etc.) for school and multiple working emulations of sensors and their communication protocols for work. I can learn the basic syntax of VHDL easily but would really appreciate any experienced people’s advice of some tricks of the trade to make the process smoother, I am worried about being the idiot who didn’t know obvious stuff. Thank you so much, I’m sure you can tell I am nervous and excited.

Hi, I would like to know which version of VHDL you are using currently and why? I personally use 2008, we made the switch from 1993 some years ago when we started a new platform. 2019 is sadly not possible yet as many tools do not support it. And we need at least 3 different vendors to support the same code base, so everyone of them need 2019 support. And I highly suspect that the simulation tool we are using also don't support 2019 features yet.

How about you? Are you stuck in 1993 because of an old code base? Or does your professor haven't touched vhdl for 20 years and so didn't knwo any 2008 features so that you still have to fill out sensitivity lists?

Are there people who can use 2019 or at least some features of it?

Coming from a comp science background, knowing how to write assembly isn't critical to being a good C programmer, since compilers generally do a better job than humans. I recently purchased my first fpga dev board, to get deeper into the hardware side of things, and I was wondering how important being able to write VHDL is when C to VHDL compilers exist. Are they generally decent at parallelizing sequential C code?

I am seeing a lot of jobs showing embedded programming plus VHDL as a desired skill set. I was wondering if anyone here had advice for a plan of self-study to gain the needed knowledge to convince an interviewer that I could handle the VHDL as it would typically appear in this sort of position. Snag I haven't done VHDL since university 20 years ago.

I don't know who all uses Emacs for VHDL but the vhdl-mode major mode is pretty great for the language. Of course, use whatever makes you the most productive. The following is from the vhdl-mode maintainer, Reto Zimmerman.

The new version vhdl-mode 3.39 is out with some enhancements and fixes:

VHDL-2019 support
Style and template enhancements
Enhanced compilation error parsing
Many indentation fixes
Emacs 28/29 support

Please check out the complete list of changes and the download link at

Please report any bugs, especially regarding indentation, as well as any missing support for VHDL-2008/2019. That's the most important features I want to keep up-to-date in vhdl-mode.

Happy coding! Reto