A12 Bionic

What Apple didn’t talk about the A12, is that it’s the first consumer available processor that supports ARMv8.3, which supports a feature called .

It essentially encrypts and decrypts certain kinds of memory access on the fly, making the phone much more hardened against hacking.

Doing all that, while gaining performance and efficiency, is extremely impressive.

This is a long post. The title is basically the Tl;Dr... if you care about the details, read on :)

I was intrigued by the Anantech comparison of the A12 with a Xeon 8176 on Spec2006, so I decided to find more spec benchmarks for other chips and run them.

Comparisons to Xeon 8192, i7 6700k, and AMD EPYC 7601 CPUs.

Notes: All results are Single-Core. If the processor is multithreaded, I tried finding the Multithreaded results. In the case of Big+Little configurations (like the A12) one Big core was used. The 6700k was the fastest Intel desktop chip I could find on the Spec2006 database.

The main takeaway here is that Apple’s A12 is approaching or exceeding the performance of these competing chips in Spec2006, with lower clock speeds and less power consumption. The A12 BIG core running at 2.5GHz beats a Xeon 8176 core running at 3.8GHz, in 9 out of 12 of Spec_Int 2006 tests, often by a large margin (up to 44%). It falls behind in 3 tests, but the deficiency is 2%, 6%, and 12%. It also comes quite close to a desktop 6700k.

No adjustment was made to normalize the results by clock speed. Core-for-Core Apple’s A12 has a a higher IPC and at least 50% better Perf/Watt than competing chips, even with the advantage of SMT on some of these! (Apple doesn’t use SMT in the A-series chips currently).

CPU Width

Monsoon (A11) and Vortex (A12) are extremely wide machines – with 6 integer execution pipelines among which two are complex units, two load units and store units, two branch ports, and three FP/vector pipelines this gives an estimated 13 execution ports, far wider than Arm’s upcoming Cortex A76 and also wider than Samsung’s M3. In fact, assuming we're not looking at an atypical shared port situation, Apple’s microarchitecture seems to far surpass anything else in terms of width, including desktop CPUs.

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By comparison, Zen and Coffee Lake have 6-wide decode + 4Int ALU per core. Here are the WikiChip block diagrams: and Even IBM's is 6-wide.

Why does this matter?

width in this case refers to Issue Width on the CPU μArch. Or "how many commands can I issue to this CPU per cycle.The wider your issue-width on a CPU, the more you instructions can be issued at once. By stacking these instructions very close to one another, you can achieve multiple instructions per Cycle, resulting in a higher IPC. This has drawbacks -- it requires longer wire length, as the electrons need to travel more to execute all the instructions and because you're doing so many things at once, the design complexity of the CPU increases. You also need to do things like reorder instructions so they'll better fit, and you need larger caches to keep the cores fed. On that note...

Cache sizes (per core) are quite large on the A12

Per core we have:

• On the A12: Each Big core has 128kB of L1$ and 8MB L2$. each Little core has 32kB of L1$ and 2MB of L2$. There’s also an additional 8 MB of SoC-wide$ (also used for other things)

• On EPYC 7601: 64kB L1$, 32kB L1D$, 512 KB L2$, 2MB shared L3$ (8 MB per 4-core complex)

• On Xeon 8176: 32kB L1$, 32kB L1D$, 1MB shared L2$, 1.375MB shared L3$

• On 6700k: 128kB L1$, 128kB L1D$, 1MB L2$, 2MB shared L3$

What Apple has done is implement a really wide μArch, combined with a metric fuckton of dedicated per-core cache, as well as a decently large 8MB Shared cache. This is likely necessary to keep the 7-wide cores fed.

RISC vs CISC

Tl;Dr: RISC vs CISC is now a moot point. At its core, CISC was all about having the CPU execute commands in as few lines of code as possible (sparing lots of memory/cache). RISC was all about diluting all commands into a series of commands which could each be executed in a single cycle, allowing for better pipelining. The tradeoff was more cache requirements and memory usage (which is why the A12 cache is so big per core), plus very compiler intensive code.

RISC is better for power consumption, but historically CISC was better for performance/$, because memory prices were high and cache sizes were limited (as larger die-area came at a high cost due to low transistor density). This is no longer the case on modern process nodes. In modern computing, both of these ISAs have evolved to the point where they now emulate each other’s features to a degree, in order to mitigate weaknesses each ISA. elaborates a bit more.

The main findings from this study are (I have access to the full paper):

1. Large performance gaps exist across the implementations, although average cycle count gaps are ≤2.5×.

2. Instruction count and mix are ISA-independent to first order.

3. Performance differences are generated by ISA-independent microarchitecture differences.

4. The energy consumption is again ISA-independent.

5. ISA differences have implementation implications, but modern microarchitecture techniques render them moot; one ISA is not fundamentally more efficient.

6. ARM and x86 implementations are simply design points optimized for different performance levels.

In general there is no computing advantage that comes from a particular ISA anymore, The advantages come from μArch choices and design optimization choices. Comparing ISA’s directly is okay, as long as your benchmark is good. Spec2006 is far better than geekbench for x-platform comparisons, and Is regularly used for ARM vs x86 server chip comparisons. Admittedly, not all the workloads are as relevant to general computing, but it does give us a good idea of where the A12 lands, compared to desktop CPUs.

Unanswered Questions:

We do not know if Apple will Scale up the A-series chips for laptop or desktop use. For one thing, the question of multicore scaling remains unanswered. Another question is how well the chips will handle a Frequency ramp-up (IPC will scale, of course, but how will power consumption fare?) This also doesn't look at scheduler performance because there's nothing to schedule on a single-thread workload running on 1 core. So Scheduler performance remains largely unknown.

But, based on power envelopes alone, Apple could already make an A12X based 3-core fanless MacBook with 11W power envelope, and throw in 6 little cores for efficiency. The battery life would be amazing. In a few generations, they might be able to do this with a higher end MacBook Pro, throwing 8 (29W) big cores, just based on the current thermals and cooling systems available.

In any case, the A12 has almost caught up to x86 desktop and server CPUs (Keep in mind that Intel’s desktop chips are faster than their laptop counterparts) Given Apple's insane rate of CPU development, and their commitment to being on the latest and best process nodes available, I predict that Apple will pull ahead in the next 2 generations, and in 3 years we could see the first ARM Mac, lining up with the potential release of Marzipan, allowing for iOS-first (and therefore ARM-first) universal apps to be deployed across the ecosystem.

Table Sources:

Edits:

• Edit 1: table formatting, grammar.

• Edit 2: added bold text to "best" in each table.

• Edit 3: from Anandtech replied suggesting some changes and I will be updating the post in a few hours.

A new result of the Apple iPhone12,3 (aka 11 Pro Max) just popped up in Geekbench 5.

• CPU:

• GPU (Metal):

Of course these are individual runs so there is some statistical noise in the data. Looking at the sub-scores, on the CPU the Image Inpainting and Ray Tracing scores stand out with +30% performance, and on the Metal test, which runs on the GPU, the Stereo Matching result stands out at double the performance.

Looking at the , this places the A13 GPU on par with the Intel Iris Plus Graphics 650/655 in the 13-inch MacBook Pro, and just above the A10X from the 2017 iPad Pros.

Just a single benchmark though, different applications may vary. Can't wait for AnandTech's review!

Sources: ,

The Apple A12 contains 6,9 billion transistors on a die of 83,3 mm². The density is 82,8 million transistors per mm², 67,4% higher than the 49,1 Mtrans/mm² of the A11. It's 211,3% higher than the 16nm FF process used by the A10, which is only 2 years old.

It will be very interesting what AMD and Nvidia could do given 3x the transistor density of 7nm FF compared to 16nm FF.

released a with floor plan today (). That means it's time for me to estimated how a more powerfull A12X could look like!

First some stats measures from the floor plan. We know that the A12 die size is 9.89mm x 8.42mm = 83.27 mm² and contains 6.9 billion transistors.

You can see the area's on this .

All the above are measured values. If you don't like speculation and calculated guess, don't read further.

The Big CPU cluster seems a little small compared to the Litte CPU cluster, a big core should be at least twice the size of a little core. But let's assume that they are right.

So let's build a A12X. I made the following modifications for my theoretical A12X.

• Doubled Big CPU cores (2 to 4 Vortex cores)

• Doubled the L2 cache (8 to 16 MB)

• Doubled the GPU (4 to 8 clusters)

• Made the NPU 50% larger (8 to 12 clusters)

• Doubled the DDR Logic interface (64-bit to 128-bit)

That would give the following values:

So far I added about 2,1 billion transistors and about 25,4mm². We also have to take interconnect into account, even Apple can't magically teleport data to different parts of the chip, so let's add 20% extra for interconnect logic (this is a guess). Also I want a larger video decoder and display pipeline for the high-res 120Hz iPad screens, so let's add 4mm² for that (plus 20% interconnect).

Now our A12X measures 83,27mm² + (25,4 mm² + 4 mm²) * 1,2 = 118,5mm², containing 9,8 billion transistors. It's 42% bigger than our A12. Sounds about right, and I think we can expect something like this from Apple in the near future.

Edit: As always, AnandTech did a much better job than both Tech Insights and me. Read their analysis here:

In light of the news today about , I think Apple could use the processor as a differentiating factor between the new 2018 models.

• 5.8 in iPhone X successor

• 6.5 in OLED iPhone

• 6.1 in LCD iPhone

I would have assumed all 3 new models would come with the new A12 chip, but now that we are hearing it will use a completely new manufacturing process, and be one of the first mass-produced 7nm chips, I could see Apple only using the A12 in the high-end OLED models, thus using the processor to differentiate the models further (in addition to the screen size/type and other features).

So it could be:

iPhone "?" ($$)

• 5.8" OLED

• A12

• New/improved "Face ID 2"

• New/improved dual camera system

iPhone "?" Plus ($$$)

• 6.5" OLED

• A12

• New/improved "Face ID 2"

• New/improved dual camera system

iPhone "?" ($)

• 6.1 LCD

• A11 Bionic

• Face ID from iPhone X

• Dual camera system from iPhone X

I think Apple will reuse a lot of the components from 2017's iPhone X on the 2018 LCD iPhone in order to save costs of developing new systems, allowing it to be a "cheap" plus sized phone will great internals. The A11 Bionic processor will still allow that iPhone to be competitive processor-wise for at least a year. Still have no clue what they will name these things though.

So what do you think?

edit: formatting

Just picked up my first Apple TV and am loving it so far. Would like to pair it with a sound bar to complete my home theatre experience, any recommendations?