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Welcome to r/Verilog

A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL

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r/ECE

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A subreddit for discussion of all things electrical and computer engineering.

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A subreddit for the discussion of all things related to the creation (not usage of!) integrated circuits, both circuit- and process-level.

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A place to ask questions, discuss topics and share projects related to Electrical Engineering.

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r/RISCV

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RISC-V (pronounced "risk-five") is a license-free, modular, extensible computer instruction set architecture (ISA). Originally designed for computer architecture research at Berkeley, RISC-V is now used in everything from $0.10 CH32V003 microcontroller chips to the pan-European supercomputing initiative, with 64 core 2 GHz workstations in between. RISC-V is suitable for custom silicon chips, as a soft core in an FPGA, or as a high performance software Virtual Machine. riscv.org

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Discussion inspired by Ben Eater's YouTube video series.

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Welcome to r/ComputerEngineering - A community for discussing computer engineering and its related areas (electrical engineering and computer science)!

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News and discussion about emulation.

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r/engineering is a forum for engineering professionals to share information, knowledge, experience related to the principles & practices of the numerous engineering disciplines. r/engineering is **NOT** for students to ask for guidance on selecting their major, or for homework / project help. Read the sidebar BEFORE posting.

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r/emacs

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The extensible, customizable, self-documenting real-time display editor.

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r/ReverseEngineering

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A moderated community dedicated to all things reverse engineering.

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r/learnprogramming

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A subreddit for all questions related to programming in any language.

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1.0k

•Posted by3 years ago

Decided to finally start learning Verilog and FPGAs. It took a couple of days, but I got a VGA text display.

Gallery

1.0k

57 comments

•Posted by2 months ago

Why are AI models so bad at writing VHDL/Verilog code?

Hello!

During my work, I have to write code for both SW and HW (FPGA).

While for SW, AI bots like ChatGPT (especially now with code interpreter) greatly reduced my load and create comprehensive, well structured code, for VHDL and Verilog, the situation is not too bright.

It takes me extensive instructions to direct AI to write a synthesizable code even for basic modules, and the mistakes he makes are very primitive, e.g. driving the signal from 2 different processes.

So my question is, why is it so different? Is it because the database for SW languages is so much bigger and more open-source, or because the models cannot comprehend the underlying rules for a synthesizable code (taking also timing into account, latency, etc..)?

Do you have any other LLM model which can make sufficiently good VHDL/Verilog code?

Thanks!

53 comments

•Posted by1 year ago

We're trying to sort this out with some of our engineers, so please humor - Do you prefer VHDL or Verilog?

Advice / Help

Any reasoning would be helpful too. We ran a poll on Twitter and got 250 responses, but wanted to see if Redditors had different ideas.

Thanks!

95 comments

145

•Posted by5 months ago

Verilog Udemy free course for FPGA beginners

Advice / Help

I have a present 🎁 for Verilog beginners who want to jump-start their skills for FPGA/ASIC Design and Verification.

Build a solid Verilog foundation so you can implement your faculty projects or pass an interview as a Junior Design/Verification Engineer!

Feel free to share the code with others (code expires in 2 days).

P.S. I would be very grateful if you could leave a nice 5* review to the course 🙏

https://www.udemy.com/course/verilog-hdl-fundamentals-for-digital-design-and-verification/?couponCode=EASYVERILOG1

145

35 comments

•Posted by3 days ago

Must learn verilog before systemverilog?

Newbie here, so I apologize if this has been discussed before. I understand that systemverilog is more of a verification language than HDL, or is it both?

If systemverilog is truly more verification then should someone new learn verilog first?

I have some experience in VHDL.

13 comments

•Posted by2 months ago

Has anyone started out with Verilog and then jumped to VHDL?

Xilinx Related

Hello, wanted to hear from those of you that started out with Verilog and then decided that VHDL was a better HDL for digital design. I've been using Verilog for a long time, but sometimes I hear people say that VHDL is better at digital design.

36 comments

131

•Posted by5 months ago

All my homies hate verilog

Discussion

131

29 comments

•Posted by23 days ago

Could someone please help me with this router design in Verilog?

Advice / Help

Hi,

I tried to write this simple router design in Verilog and I have tested each individual modules and each module works. You can check this block diagram to get an idea: https://i.imgur.com/hzVAipW.png

Please note that I have made some little changes to the block diagram but the block diagram doesn't show it, but overall the shown block diagram is good.

The problem is that the design does not work. The FIFOs don't output anything. Honestly, I have checked it many times for the last many days and everything looks okay.

Could you please give it a look? I understand that it's not easy to check this type of design. So, I will be really, really appreciate it if you can help me.

You can use either of the two links below to access the code. You can edit the code using Link #2.

Link #1: https://gist.github.com/painterguy1995/7ea1a9d9723205f96b62db9bd66064c1

Link #2: https://codefile.io/f/beGvt3GWnA

20 comments