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r/VHDL

2.9k members

Do you have any VHDL design you are proud of, or do you need help with some code this is the place for it.

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r/FPGA

43.9k members

A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL

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r/ECE

174k members

A subreddit for discussion of all things electrical and computer engineering.

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r/ElectricalEngineering

185k members

A place to ask questions, discuss topics and share projects related to Electrical Engineering.

Computer Programming

The extensible, customizable, self-documenting real-time display editor.

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r/PicoBlaze

17 members

This is an unofficial (not affiliated with Xilinx) community about Xilinx PicoBlaze, an open-source CPU written entirely in VHDL and intended to be synthesized on FPGAs (it is a so-called soft-processor). If you have some assembly-language program you would like to be added into the list of examples in PicoBlaze Simulator in JavaScript, feel free to share it here.

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r/ProgrammerHumor

3.1m members

For anything funny related to programming and software development.

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r/AskElectronics

689k members

A subreddit for practical questions about component-level electronic circuits: design, repair, component buying, test gear and tools.

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r/beneater

16.3k members

Discussion inspired by Ben Eater's YouTube video series.

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r/electronics

920k members

Discussion and news about component-level electronic circuits.

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r/ComputerEngineering

29.3k members

Welcome to r/ComputerEngineering - A community for discussing computer engineering and its related areas (electrical engineering and computer science)!

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490

•Posted by7 months ago

This is a real data type that is the primary data format in a language called VHDL. This is not a joke.

Advanced

490

68 comments

•Posted by2 months ago

Why are AI models so bad at writing VHDL/Verilog code?

Hello!

During my work, I have to write code for both SW and HW (FPGA).

While for SW, AI bots like ChatGPT (especially now with code interpreter) greatly reduced my load and create comprehensive, well structured code, for VHDL and Verilog, the situation is not too bright.

It takes me extensive instructions to direct AI to write a synthesizable code even for basic modules, and the mistakes he makes are very primitive, e.g. driving the signal from 2 different processes.

So my question is, why is it so different? Is it because the database for SW languages is so much bigger and more open-source, or because the models cannot comprehend the underlying rules for a synthesizable code (taking also timing into account, latency, etc..)?

Do you have any other LLM model which can make sufficiently good VHDL/Verilog code?

Thanks!

53 comments

•Posted by1 year ago

We're trying to sort this out with some of our engineers, so please humor - Do you prefer VHDL or Verilog?

Advice / Help

Any reasoning would be helpful too. We ran a poll on Twitter and got 250 responses, but wanted to see if Redditors had different ideas.

Thanks!

95 comments

•Posted by2 months ago

Has anyone started out with Verilog and then jumped to VHDL?

Xilinx Related

Hello, wanted to hear from those of you that started out with Verilog and then decided that VHDL was a better HDL for digital design. I've been using Verilog for a long time, but sometimes I hear people say that VHDL is better at digital design.

36 comments

•Posted by11 days ago

Latest vhdl-mode package for Emacs

I don't know who all uses Emacs for VHDL but the vhdl-mode major mode is pretty great for the language. Of course, use whatever makes you the most productive. The following is from the vhdl-mode maintainer, Reto Zimmerman.

The new version vhdl-mode 3.39 is out with some enhancements and fixes:
VHDL-2019 support Style and template enhancements Enhanced compilation error parsing Many indentation fixes Emacs 28/29 support
Please check out the complete list of changes and the download link at
http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html
Please report any bugs, especially regarding indentation, as well as any missing support for VHDL-2008/2019. That's the most important features I want to keep up-to-date in vhdl-mode.
Happy coding! Reto

18 comments

•Posted by5 months ago

Learning VHDL for FPGAs

Hi everyone,

I'm a first year EE student, and I just finished my first logic circuits class. I loved it so much that I asked my teacher for what I should do to learn more on the subject, and he told me wait for the next class. The next electronics class is in 2 years...

So I want to get into microelectronics, and I heard from seniors I should learn VHDL and I should goof around with FPGAs, but I have no idea where to start. Right now I know basic logic components, as well as sequential circuits. (I study in french I don't know the right english terms for it sorry)

Some labs I've done include a 4bit ALU with add/sub and 3 flags, and also my final big boss lab was an alarm system with a movement detector, so there was quite a bit of sequential logic there. Also, I have a macbook so I don't know if that's important for HDL.

If you know where I should start, please let me know! Thanks

49 comments

•Posted by1 year ago

Why do you prefer VHDL?

I've done VHDL, Verilog, and SystemVerilog. I write pretty much exclusively SystemVerilog these days.

After a decade of experience, I've come to a soft conclusion that Verilog is so much better than VHDL. I've seen many comparisons where people show pros/cons and conclude that one is not better than the other. This certainly sounds like a mature conclusion. But in my actual experience, I just don't see how / when / why anyone would prefer VHDL. It just about always takes me much longer to write equivalent VHDL code.

Here are the most commonly cited advantages I hear for VHDL (along with my thoughts):

VHDL forces you to write more correct code. Sure, but at what cost? In my experience, once you get past beginner coder, you're not often going to be making simple typing / width errors. And they're easy to debug when you do. To me, it seems like a bad trade-off to force (sometime complicated) casting upon the user. I don't see how the benefits outweigh the overhead cost in the long-run. Just let me write what I want to write, dang it!
VHDL has library support. I actually see this as a disadvantage. In order to do simple things that Verilog and SystemVerilog has built into the language, you have to import libraries. And there's confusing overlapping implementations between libraries at times. And nobody ever seems to totally know what functions are in what libraries off the top of their heads. This slows down development. You want something like a simple 2D vector? You've gotta create a custom data type and import it everywhere. Furthermore, I find that libraries tend to get out of control over time, and end up bloating up projects.
VHDL is more easy to understand. No its not.
VHDL is deterministic. Referring to a simulation timestep. Okay, I'll give you this one. SystemVerilog has the cumbersome clocking block to deal with this issue.

Overall, I don't see how the benefits ever outweigh the cons. Maybe it has to do with how I think, or where I am in my career? Once I come up with a conceptual solution, I want to be able to translate that into HDL as fast and effortlessly as possible. But VHDL just seems to get in the way in this process, sucking the joy out of the design process.

Please, if you prefer VHDL, change my mind! I actually am open to other perspectives here!

73 comments