I've done VHDL, Verilog, and SystemVerilog. I write pretty much exclusively SystemVerilog these days.

After a decade of experience, I've come to a soft conclusion that Verilog is so much better than VHDL. I've seen many comparisons where people show pros/cons and conclude that one is not better than the other. This certainly sounds like a mature conclusion. But in my actual experience, I just don't see how / when / why anyone would prefer VHDL. It just about always takes me much longer to write equivalent VHDL code.

Here are the most commonly cited advantages I hear for VHDL (along with my thoughts):

1. VHDL forces you to write more correct code. Sure, but at what cost? In my experience, once you get past beginner coder, you're not often going to be making simple typing / width errors. And they're easy to debug when you do. To me, it seems like a bad trade-off to force (sometime complicated) casting upon the user. I don't see how the benefits outweigh the overhead cost in the long-run. Just let me write what I want to write, dang it!

2. VHDL has library support. I actually see this as a disadvantage. In order to do simple things that Verilog and SystemVerilog has built into the language, you have to import libraries. And there's confusing overlapping implementations between libraries at times. And nobody ever seems to totally know what functions are in what libraries off the top of their heads. This slows down development. You want something like a simple 2D vector? You've gotta create a custom data type and import it everywhere. Furthermore, I find that libraries tend to get out of control over time, and end up bloating up projects.

3. VHDL is more easy to understand. No its not.

4. VHDL is deterministic. Referring to a simulation timestep. Okay, I'll give you this one. SystemVerilog has the cumbersome clocking block to deal with this issue.

Overall, I don't see how the benefits ever outweigh the cons. Maybe it has to do with how I think, or where I am in my career? Once I come up with a conceptual solution, I want to be able to translate that into HDL as fast and effortlessly as possible. But VHDL just seems to get in the way in this process, sucking the joy out of the design process.

Please, if you prefer VHDL, change my mind! I actually am open to other perspectives here!