Posts about Verilog
There's some great resources pinned in this sub, but for professional reasons (credit hour tracking) I'm looking for some courses with associated certificates/credit hours, etc.
What I've found so far are several courses from University of Colorado - Boulder (via Coursera) that seem interesting. Also quite a few on Udemy.
I'm curious if anyone has actually taken these courses and can vouch for them? I don't trust the reviews from the sites. Also if it makes any difference I'm going to begin some projects working with Lattice (Certus-NX), would be cool if there was a course that used Radiant to get me familiar with their environment.
The Cyclic Redundancy Code(CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to digital data. And blue-crc repo provides a parallel, pipelined and highly-parameterized hardware implementation of CRC targeting high-throughput applications, such as network transmission.
CRC is a mature and widely-adopted error-detecting technology, and there have been numerous hardware implementations of it. However, most existing hardware designs are either implemented using pure combinational logic or are only designed to process input data byte-by-byte serially, which results in extremely low throughput. Other designs targeting high-performance applications lack proper parameterization and only support some specific CRC configurations. Blue-crc aims to solve these problems by providing both high-throughput and well-parameterized CRC hardware implementation.
Complete CRC Configuration: the implementation supports complete CRC configuration parameters, including polynomial, initVal(the initial CRC value), finalXor(the result is xor’d with this value if desired), reflectData(if True, the input bit order is reversed), and reflectRemainder(if True, the result bit order is reversed).
Standard Interfaces: The input interface follows AxiStream protocol, with a parameterized data width. The output CRC result is guarded by the basic handshake protocol.
Parallel: The IP is designed to process multiple bytes per cycle.
Fully Pipelined: The implementation takes in raw data and produces results every cycle.
High Throughput: The implementation, configured with 256-bit input and 32-bit CRC output, runs at 500MHz on Xilinx xcvu9p FPGA.
For BSV users, you can import our codes and instantiate CrcAxiStream interface in your design directly. Besides, we provide a script to generate custom Verilog CRC implementation automatically. If you are interested in high-performance CRC hardware acceleration, it’s worth giving it a try. We are also open to any recommendations for further improving our designs.
GitHub: https://github.com/datenlord/blue-crc
References: https://ieeexplore.ieee.org/abstract/document/5501903
I'm specifically looking for resources that detail how to take advantage of the structure of FPGAs (i.e. efficient use of logic blocks and BRAMs) to reduce power, area, and latency, and also remain somewhat vendor-independent. Stuff like partitioning combinational circuits into 4-bit blocks, maximizing parallelism in the synthesized circuit wherever possible, etc.
Basically something along the lines of this but more in-depth?
EDIT: Resources on HLS are greatly appreciated since I'm going to have to use it in the later stages of my project, but I'd highly prefer ones that concern optimizing RTL design.