This is about a digital circuit. For an electronic circuit that handles analog signals see Electronic mixer.

In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar.

Although adders can be constructed for many numerical representations, such as binary-coded decimal or excess-3, the most common adders operate on binary numbers. In cases where two's complement or ones' complement is being used to represent negative numbers, it is trivial to modify an adder into an adder–subtractor. Other signed number representations require a more complex adder.

Half adder[link]

Half Adder logic diagram

The half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder.^[1]

Full adder[link]

Schematic symbol for a 1-bit full adder with C_in and C_out drawn on sides of block to emphasize their use in a multi-bit adder

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and C_in; A and B are the operands, and C_in is a bit carried in from the next less significant stage.^[2] The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The circuit produces a two-bit output sum typically represented by the signals C_out and S, where Failed to parse (Missing texvc executable; please see math/README to configure.): \mathrm{sum} = 2 \times C_{out} + S . The one-bit full adder's truth table is:

Full-adder logic diagram

A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with Failed to parse (Missing texvc executable; please see math/README to configure.): S = A \oplus B \oplus C_{in}

and Failed to parse (Missing texvc executable; please see math/README to configure.): C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B))

.

In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. In this light, C_out can be implemented as Failed to parse (Missing texvc executable; please see math/README to configure.): C_{out} = (A \cdot B) \oplus (C_{in} \cdot (A \oplus B)) .

A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting C_i to the other input and OR the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and C_i, and C_out could be made the three-bit majority function of A, B, and C_i.

More complex adders[link]

Ripple carry adder[link]

4-bit adder with logic gates shown

It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a C_in, which is the C_out of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.

The layout of a ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 * 2 (for carry propagation in later adders) = 65 gate delays. A design with alternating carry polarities and optimized AND-OR-Invert gates can be about twice as fast.^[3]

Carry-lookahead adders[link]

4-bit adder with carry lookahead

To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry-lookahead adders. They work by creating two signals (P and G) for each bit position, based on if a carry is propagated through from a less significant bit position (at least one input is a '1'), a carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0'). In most cases, P is simply the sum output of a half-adder and G is the carry output of the same adder. After P and G are generated the carries for every bit position are created. Some advanced carry-lookahead architectures are the Manchester carry chain, Brent–Kung adder, and the Kogge–Stone adder.

Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry bypass adder which will determine P and G values for each block rather than each bit, and the carry select adder which pre-generates sum and carry values for either possible carry input to the block.

Other adder designs include the carry-save adder, carry-select adder, conditional-sum adder, carry-skip adder, and carry-complete adder.

Lookahead carry unit[link]

A 64-bit adder

By combining multiple carry lookahead adders even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of LCUs.

3:2 compressors[link]

We can view a full adder as a 3:2 lossy compressor: it sums three one-bit inputs, and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of 101 results in an output of 1+0+1=10 (decimal number '2'). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 lossy compressor, compressing four possible inputs into three possible outputs.

Such compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the carry-save adder. If the addends are four or more, more than one layer of compressors is necessary and there are various possible design for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.

See also[link]

• Category:Adders
• Additron tube
• Adding machine
• Subtractor
• Binary multiplier
• Serial binary adder
• Half subtractor

References[link]

1. ^ Geoffrey A. Lancaster (2004). Excel HSC Software Design and Development. Pascal Press. p. 180. ISBN 9781741251753. http://books.google.com/books?id=PZkDpS4m0fMC&pg=PA180. 
2. ^ M. Morris Mano, Digital Logic and Computer Design, Prentice-Hall 1979, ISBN 0-13-21450-3 pp.119-123
3. ^ Burgess, N. (2011). "Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI". 20th IEEE Symposium on Computer Arithmetic: 103–111. http://ieeexplore.ieee.org/Xplore/login.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F5991607%2F5992089%2F05992115.pdf%3Farnumber%3D5992115&authDecision=-203. 

External links[link]

• Hardware algorithms for arithmetic modules, includes description of several adder layouts with figures.