Arria

Arria (also Arria Major) was a woman in ancient Rome. Her husband, Caecina Paetus, was ordered by the emperor Claudius to commit suicide for his part in a rebellion but was not capable of forcing himself to do so. Arria wrenched the dagger from him and stabbed herself, then returned it to her husband, telling him that it didn't hurt ("Non dolet, Paete!"). Her story was recorded in the letters of Pliny the Younger, who obtained his information from Arria's granddaughter, Fannia.

Pliny records that Arria's son died at the same time as Caecina Paetus was quite ill. She apparently arranged and planned the child's funeral without her husband even knowing of his death. Every time she visited her husband, Arria told him that the boy was improving. If emotion threatened to get the better of her, she excused herself from the room and would, in Pliny's words, "give herself to sorrow", and then return to her husband with a calm demeanor.

After the rebellion against Claudius led by Lucius Arruntius Camillus Scribonianus in 42. AD, Scribonianus was killed and Caecina was taken to Rome as a prisoner for conspiring with him. Arria begged the captain of the ship to allow her to join him on board. She claimed that if a consular Roman man was allowed slaves to take care of him, then she should save them the trouble and look after him herself. The captain refused, so Arria followed the great ship in a small fishing boat all the way to Rome.

Field-programmable gate array

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare.)

FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

Technical design

Contemporary field-programmable gate arrays (FPGAs) have large resources of logic gates and RAM blocks to implement complex digital computations. As FPGA designs employ very fast I/Os and bidirectional data buses it becomes a challenge to verify correct timing of valid data within setup time and hold time. Floor planning enables resources allocation within FPGAs to meet these time constraints. FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.