The Intriguing 6502 Microprocessor!

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• published: 15 Jun 2014
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I wanted to make a video about the 6502 because, besides being the workhorse of the Nintendo Entertainment System, Commodore 64, Atari 2600, Apple IIe, and a lot of other important 8-bit microcomputers of the 1980s, it is a very interesting little processor for a number of reasons. 1.) It is basically the first reduced instruction set computer (RISC) consumer processor of its time. When compared the 8086, Z80 and the 6800, the 6502 has less instructions overall, making learning about how to program the processor rather easy. The 6502 does not contain any "oddball" or otherwise superfluous instructions; it has 151 documented opcodes that only do the most essential operations required for writing any level of complex host software. 2.) It has 1:1 CPU clock cycle to memory bus access timings. This means that system memory can be accessed every CPU clock cycle. In comparison to the Z80 and 8086/8088, the CPU has to use at least 4 clock cycles to do one memory cycle access. The 6800 had 1:1 CPU-to-memory bus clocking, but does not use the clock cycles as efficiently as the 6502 for most instructions. 3.) Efficient addressing mode instructions. The absolute indexed addressing mode of the 6502 allows an instruction with a 16-bit displacement to be added to an 8-bit internal index register to fetch a byte from memory into the CPU with no additional latency. This is a big deal, since I know of no other 8-bit processors prior to the 6502 that can do an effective address calculation for free. The 6502 uses a type of pipelining so that while the processor is fetching the hi byte of the displacement, it adds the index register to the lo displacement to calculate the effective address, providing the page boundary is not crossed. This type of optimization increases the throughput of 6502 absolute indexed instructions by 25%, while maintaining 0% wasted memory bus cycles. 4.) Powerful indirect addressing mode instructions. Although the 6502 only has 2 internal 8-bit index registers, the entire zero page of memory can be used as an additional 128 address registers of 16-bits each. Using an 8-bit displacement with an indirect addressing instruction, the index registers can be either used to pre-index the zero page address to fetch the full 16-bit effective address from, or it can be post-added to the 16-bit value at a static zero-page address. The post-indexed indirect mode is by far the most popular, as it allows an index register to be used as an 8-bit array index counter, while having random access to up to 128 system-wide arrays. In addition, the post-indexed indirect mode uses the same effective address calculation pipelining that was mentioned previously, offering a throughput boost of 20% over the pre-indexed indirect mode, providing a page boundary is not crossed of course. 5.) Useful undocumented opcodes. The 6502 has to be the only processor I have ever known to have 1/4 of its entire opcode map dedicated to the operation of instruction groups that overlap others in a useful way, all by incredible accident of great design engineering! Of course the practical usefulness of these instructions varies. Really it is about the art of optimizing your algorithm for timing constraints that makes these undocumented opcodes an interesting challenge to implement. One big advantage to using these opcodes is that they allow access to 3 addressing modes not normally available for the RMW instruction group- that is the preindex and postindex indirect modes, and also the absolute-Y-indexed mode. if you do not need to worry about destroying the contents of the accumulator, the undocumented opcodes give you access to all those other normally-unavailable addressing modes. LAX- load A and X instructions are also found in this same undocumented group. You can load two 6502 registers simultaneously, saving a couple of clock cycles. SAX- supposedly performs a logical AND between A & X, then stores the result to memory. This is possible because the 6502 is built with NMOS technology, with no active pull-up transistors in the circuitry (so the 0s cancel out the 1s). Other undocumented 6502 opcodes are mostly treated as multi-byte NOPs, meaning that the instruction will use the selected addressing mode to determine the instruction size, but no work is done other than the program counter being advanced, and clock cycles being consumed. These codes are handy for embedding a 1-byte instruction into the beginning of a loop (i.e., within the immediate field of a 2-byte NOP) where you do not want to execute the instruction on initial entry. Another use of these NOP-codes is to read the address of a memory-mapped IO port that needs acknowledgement via read, but you don't need to save the read contents anywhere. Other uses for multi-byte NOPs could be in creating timing loops. 3 clock cycle NOPs can be made out of zero page addressing mode NOPs.