Back with another video, this time of a very kooky kind of memory that involves storing bits in a long slow delay medium arranged in a loop (historically made out of things like mercury storing acoustic pulses, here made out of a long inverter chain). While it has some very redeeming features in terms of its read/write capabilities and its memory density, the access times are quite poor and the load it would apply to a minecraft server is probably pretty high (especially if you were trying to make an array big enough to actually be useful for something). As a rough comparison, a programmable ROM cell in minecraft can be fit into a repeating area as small as 2x3 (6 blocks) and a standard D-latch based read/write cell fits into a repeating space of 9x4 (36 blocks) with my best design so far. These sizes are both tile-able, meaning they have the requisite spaces between them that you can sandwich such cells side by side without problems. With these standard cells, gaining write capability involves a cell about 6x the area of a read-only cell, which correlates pretty closely to how SRAM is implemented in actual silicon. Minecraft delay line memory, however, takes up an area of about 8-10 blocks per "cell", meaning you're only paying about a 20-30% premium over a read-only cell to gain write capability. You pay for the privilege though, in the form of crappy access times (probably 8-10 seconds or more for a worthwhile size) and a probably impractical amount of server load. I <b>...</b>