The PowerPC A2 is a massively multicore capable and multithreaded 64-bit Power Architecture processor core designed by IBM using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz version with 16 cores consuming 65 W to a less powerful, four core version, consuming 20 W at 1.4 GHz. Each A2 core is capable of four-way multithreading and have 16+16 instruction and data cache per core. All core variants execute instructions in-order.

The PowerEN (Power Edge of Network), or the "wire-speed processor", is designed as hybrid between regular networking processors, doing switching and routing and a typical server processor, that is manipulating and packaging data. It was revealed February 8 2010, at ISSCC 2010.

Each chip has 8 MB of cache as well a multitude of task-specific engines besides the general-purpose processors, such as XML, cryptography, compression and regular expression accelerators each with MMUs of their own, four 10 Gigabit Ethernet ports and two PCIe lanes. Up to four chips can be linked in a SMP system without any additional support chips. The chips are said to be extremely complex, and use 1.43 billion transistors on a die size of 428 mm² fabricated using a 45 nm process.