Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM (electrically erasable programmable read-only memory) and must be erased in fairly large blocks before these can be rewritten with new data. The high density NAND type must also be programmed and read in (smaller) blocks, or pages, while the NOR type allows a single machine word (byte) to be written or read independently.
The NAND type is primarily used in memory cards, USB flash drives, solid-state drives, and similar products, for general storage and transfer of data. The NOR type, which allows true random access and therefore direct code execution, is used as a replacement for the older EPROM and as an alternative to certain kinds of ROM applications. However, NOR flash memory may emulate ROM primarily at the machine code level; many digital designs need ROM (or PLA) structures for other uses, often at significantly higher speeds than (economical) flash memory may achieve. NAND or NOR flash memory is also often used to store configuration data in numerous digital products, a task previously made possible by EEPROMs or battery-powered static RAM.
Example applications of both types of flash memory include personal computers, PDAs, digital audio players, digital cameras, mobile phones, synthesizers, video games, scientific instrumentation, industrial robotics, medical electronics, and so on. In addition to being non-volatile, flash memory offers fast read access times, as fast as dynamic RAM, although not as fast as static RAM or ROM. Its mechanical shock resistance helps explain its popularity over hard disks in portable devices; as does its high durability, being able to withstand high pressure, temperature, immersion in water etc.[1]
Although flash memory is technically a type of EEPROM, the term "EEPROM" is generally used to refer specifically to non-flash EEPROM which is erasable in small blocks, typically bytes. Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over old-style EEPROM when writing large amounts of data.[citation needed] Flash memory now costs far less than byte-programmable EEPROM and has become the dominant memory type wherever a significant amount of non-volatile, solid state storage is needed.
Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba circa 1980.[2][3] According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shōji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera. Dr. Masuoka presented the invention at the IEEE 1984 International Electron Devices Meeting (IEDM) held in San Francisco.
Intel Corporation saw the massive potential of the invention and introduced the first commercial NOR type flash chip in 1988.[4] NOR-based flash has long erase and write times, but provides full address and data buses, allowing random access to any memory location. This makes it a suitable replacement for older read-only memory (ROM) chips, which are used to store program code that rarely needs to be updated, such as a computer's BIOS or the firmware of set-top boxes. Its endurance may be from as little as 100 erase cycles for an on-chip flash memory,[5] to a more typical 10,000 or 100,000 erase cycles, up to 1,000,000 erase cycles.[6] NOR-based flash was the basis of early flash-based removable media; CompactFlash was originally based on it, though later cards moved to less expensive NAND flash.
Toshiba announced NAND flash at the 1987 International Electron Devices Meeting. It has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR flash; it also has up to ten times the endurance of NOR flash. However, the I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This made NAND flash unsuitable as a drop-in replacement for program ROM, since most microprocessors and microcontrollers required byte-level random access. In this regard, NAND flash is similar to other secondary data storage devices, such as hard disks and optical media, and is thus very suitable for use in mass-storage devices, such as memory cards. The first NAND-based removable media format was SmartMedia in 1995, and many others have followed, including MultiMediaCard, Secure Digital, Memory Stick and xD-Picture Card. A new generation of memory card formats, including RS-MMC, miniSD and microSD, and Intelligent Stick, feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm2, with a thickness of less than 1 mm. microSD capacities range from 64 MB to 64 GB, as of May 2011.[7]
Flash memory stores information in an array of memory cells made from floating-gate transistors. In traditional single-level cell (SLC) devices, each cell stores only one bit of information. Some newer flash memory, known as multi-level cell (MLC) devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells.
The floating gate may be conductive (typically polysilicon in most kinds of flash memory) or non-conductive (as in SONOS flash memory).[8]
In flash memory, each memory cell resembles a standard MOSFET, except the transistor has two gates instead of one. On top is the control gate (CG), as in other MOS transistors, but below this there is a floating gate (FG) insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, any electrons placed on it are trapped there and, under normal conditions, will not discharge for many years. When the FG holds a charge, it screens (partially cancels) the electric field from the CG, which modifies the threshold voltage (VT) of the cell (more voltage has to be applied to the CG to make the channel conduct). For read-out, a voltage intermediate between the possible threshold voltages is applied to the CG, and the MOSFET channel's conductivity tested (if it's conducting or insulating), which is influenced by the FG. The current flow through the MOSFET channel is sensed and forms a binary code, reproducing the stored data. In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.
NOR flash memory wiring and structure on silicon
In NOR gate flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a NOR gate: when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR Flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device. The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product.[9]
Programming a NOR memory cell (setting it to logical 0), via hot-electron injection.
Erasing a NOR memory cell (setting it to logical 1), via quantum tunneling.
A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure:
- an elevated on-voltage (typically >5 V) is applied to the CG
- the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS transistor)
- the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called hot-electron injection
To erase a NOR flash cell (resetting it to the "1" state), a large voltage of the opposite polarity is applied between the CG and source terminal, pulling the electrons off the FG through quantum tunneling. Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can only be performed on a block-wise basis; all the cells in an erase segment must be erased together. Programming of NOR cells, however, can generally be performed one byte or word at a time.
Despite the need for high programming and erasing voltages, virtually all flash chips today require only a single supply voltage, and produce the high voltages via on-chip charge pumps.
NAND flash memory wiring and structure on silicon
NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors' VT) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array.
To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.
Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistor below the size where they can be made reliably, to the size where further reductions would increase the number of faults faster than it would increase the total storage available.
NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB storage devices known as USB flash drives, as well as most memory card formats and solid-state drives available today.
One limitation of flash memory is that although it can be read or programmed a byte or a word at a time in a random access fashion, it can only be erased a "block" at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations, but does not offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written values. For example, a nibble value may be erased to 1111, then written e.g. as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. Essentially, erasure sets all bits to 1, and programming can only clear bits to 0. File systems designed for flash devices can make use of this capability, for example to represent sector metadata.
Although data structures in flash memory cannot be updated in completely general ways, this allows members to be "removed" by marking them as invalid. This technique may need to be modified for multi-level cell devices, where one memory cell holds more than one bit.
Common flash devices such as USB flash drives and memory cards provide only a block-level interface, or flash translation layer (FTL), which writes to a different cell each time to wear-level the device. This prevents incremental writing within a block, however it does not help the device from being prematurely worn out by poorly designed systems. For example, nearly all consumer devices ship formatted with the MS-FAT file system, which pre-dates flash memory, having been designed for DOS and disk media.
Another limitation is that flash memory has a finite number of program-erase cycles (typically written as P/E cycles). Most commercially available flash products are guaranteed to withstand around 100,000 P/E cycles, before the wear begins to deteriorate the integrity of the storage.[10] Micron Technology and Sun Microsystems announced an SLC NAND flash memory chip rated for 1,000,000 P/E cycles on 17 December 2008.[11]
The guaranteed cycle count may apply only to block zero (as is the case with TSOP NAND devices), or to all blocks (as in NOR). This effect is partially offset in some chip firmware or file system drivers by counting the writes and dynamically remapping blocks in order to spread write operations between sectors; this technique is called wear leveling. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called bad block management (BBM). For portable consumer devices, these wearout management techniques typically extend the life of the flash memory beyond the life of the device itself, and some data loss may be acceptable in these applications. For high reliability data storage, however, it is not advisable to use flash memory that would have to go through a large number of programming cycles. This limitation is meaningless for 'read-only' applications such as thin clients and routers, which are programmed only once or at most a few times during their lifetimes.
The method used to read NAND flash memory can cause other cells near the cell being read to change over time if the surrounding cells of the block are not rewritten. This is generally in the hundreds of thousands of reads without a rewrite of those cells. The error does not appear when reading the original cell, but rather shows up when finally reading one of the surrounding cells. If the flash controller does not track the total number of reads across the whole storage device and rewrite the surrounding data periodically as a precaution, a read disturb error will likely occur, with data loss as a result.[12][13]
The low-level interface to flash memory chips differs from those of other memory types such as DRAM, ROM, and EEPROM, which support bit-alterability (both zero to one and one to zero) and random access via externally accessible address buses.
NOR memory has an external address bus for reading and programming. For NOR memory, reading and programming are random-access, and unlocking and erasing are block-wise. For NAND memory, reading and programming are page-wise, and unlocking and erasing are block-wise.
Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly from the NOR flash without needing to be copied into RAM first. NOR flash may be programmed in a random-access manner similar to reading. Programming changes bits from a logical one to a zero. Bits that are already zero are left unchanged. Erasure must happen a block at a time, and resets all the bits in the erased block back to one. Typical block sizes are 64, 128, or 256 KB.
Bad block management is a relatively new feature in NOR chips. In older NOR devices not supporting bad block management, the software or device driver controlling the memory chip must correct for blocks that wear out, or the device will cease to work reliably.
The specific commands used to lock, unlock, program, or erase NOR memories differ for each manufacturer. To avoid needing unique driver software for every device made, special Common Flash Memory Interface (CFI) commands allow the device to identify itself and its critical operating parameters.
Besides using NOR memory as random-access ROM, you can use it as a storage device, by taking advantage of random-access programming. Some devices offer read-while-write functionality so that code continues to execute even while a program or erase operation is occurring in the background. For sequential data writes, NOR flash chips typically have slow write speeds, compared with NAND flash.
NAND flash architecture was introduced by Toshiba in 1989. These memories are accessed much like block devices, such as hard disks or memory cards. Each block consists of a number of pages. The pages are typically 512[14] or 2,048 or 4,096 bytes in size. Associated with each page are a few bytes (typically 1/32 of the data size) that can be used for storage of an error correcting code (ECC) checksum.
Typical block sizes include:
- 32 pages of 512+16 bytes each for a block size of 16 KB
- 64 pages of 2,048+64 bytes each for a block size of 128 KB[15]
- 64 pages of 4,096+128 bytes each for a block size of 256 KB[16]
- 128 pages of 4,096+128 bytes each for a block size of 512 KB.
While reading and programming is performed on a page basis, erasure can only be performed on a block basis.[17] Number of Operations (NOPs) is the number of times the pages can be programmed. So far, this number for MLC flash is always one, whereas for SLC flash, it is four.[citation needed]
NAND devices also require bad block management by the device driver software, or by a separate controller chip. SD cards, for example, include controller circuitry to perform bad block management and wear leveling. When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller. A number of blocks on the flash chip may be set aside for storing mapping tables to deal with bad blocks, or the system may simply check each block at power-up to create a bad block map in RAM. The overall memory capacity gradually shrinks as more blocks are marked as bad.
NAND relies on ECC to compensate for bits that may spontaneously fail during normal device operation. A typical ECC will correct a one-bit error in each 2048 bits (256 bytes) using 22 bits of ECC code, or a one-bit error in each 4096 bits (512 bytes) using 24 bits of ECC code.[18] If the ECC cannot correct the error during read, it may still detect the error. When doing erase or program operations, the device can detect blocks that fail to program or erase and mark them bad. The data is then written to a different, good block, and the bad block map is updated.
Most NAND devices are shipped from the factory with some bad blocks. These are typically marked according to a specified bad block marking strategy. By allowing some bad blocks, the manufacturers achieve far higher yields than would be possible if all blocks had to be verified good. This significantly reduces NAND flash costs and only slightly decreases the storage capacity of the parts.
When executing software from NAND memories, virtual memory strategies are often used: memory contents must first be paged or copied into memory-mapped RAM and executed there (leading to the common combination of NAND + RAM). A memory management unit (MMU) in the system is helpful, but this can also be accomplished with overlays. For this reason, some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a non-volatile data storage area.
NAND sacrifices the random-access and execute-in-place advantages of NOR. NAND is best suited to systems requiring high capacity data storage. It offers higher densities, larger capacities, and lower cost. It has faster erases, sequential writes, and sequential reads.
A group called the Open NAND Flash Interface Working Group (ONFI) has developed a standardized low-level interface for NAND flash chips. This allows interoperability between conforming NAND devices from different vendors. The ONFI specification version 1.0[19] was released on 28 December 2006. It specifies:
- a standard physical interface (pinout) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages
- a standard command set for reading, writing, and erasing NAND flash chips
- a mechanism for self-identification (comparable to the serial presence detection feature of SDRAM memory modules)
The ONFI group is supported by major NAND flash manufacturers, including Hynix, Intel, Micron Technology, and Numonyx, as well as by major manufacturers of devices incorporating NAND flash chips.[20]
A group of vendors, including Intel, Dell, and Microsoft, formed a Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group.[21] The goal of the group is to provide standard software and hardware programming interfaces for nonvolatile memory subsystems, including the "flash cache" device connected to the PCI Express bus.
NOR and NAND flash differ in two important ways:
- the connections of the individual memory cells are different
- the interface provided for reading and writing the memory is different (NOR allows random-access for reading, NAND allows only page access)
These two are linked by the design choices made in the development of NAND flash. A goal of NAND flash development was to reduce the chip area required to implement a given capacity of flash memory, and thereby to reduce cost per bit and increase maximum chip capacity so that flash memory could compete with magnetic storage devices like hard disks.[citation needed]
NOR and NAND flash get their names from the structure of the interconnections between memory cells.[22] In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a NAND gate. The series connections consume less space than parallel ones, reducing the cost of NAND flash. It does not, by itself, prevent NAND cells from being read and programmed individually.
When NOR flash was developed, it was envisioned as a more economical and conveniently rewritable ROM than contemporary EPROM and EEPROM memories. Thus random-access reading circuitry was necessary. However, it was expected that NOR flash ROM would be read much more often than written, so the write circuitry included was fairly slow and could only erase in a block-wise fashion. On the other hand, applications that use flash as a replacement for disk drives do not require word-level write address, which would only add to the complexity and cost unnecessarily.[citation needed]
Because of the series connection and removal of wordline contacts, a large grid of NAND flash memory cells will occupy perhaps only 60% of the area of equivalent NOR cells[23] (assuming the same CMOS process resolution, e.g. 130nm, 90 nm, 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential-accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random-access of NAND flash memory impossible, but the goal of NAND flash was to replace hard disks, not to replace ROMs.
The write endurance of SLC floating-gate NOR flash is typically equal to or greater than that of NAND flash, while MLC NOR and NAND flash have similar endurance capabilities. Example Endurance cycle ratings listed in datasheets for NAND and NOR flash are provided.
- SLC NAND flash is typically rated at about 100k cycles (Samsung OneNAND KFW4G16Q2M)
- MLC NAND flash used to be rated at about 5–10k cycles (Samsung K9G8G08U0M) but is now typically 1k – 3k cycles
- TLC NAND flash is typically rated at about 100–500 cycles
- SLC floating-gate NOR flash has typical endurance rating of 100k to 1M cycles (Numonyx M58BW 100k; Spansion S29CD016J 1,000k)
- MLC floating-gate NOR flash has typical endurance rating of 100k cycles (Numonyx J3 flash)
However, by applying certain algorithms and design paradigms such as wear leveling and memory over-provisioning, the endurance of a storage system can be tuned to serve specific requirements.[24]
Because of the particular characteristics of flash memory, it is best used with either a controller to perform wear leveling and error correction or specifically designed flash file systems, which spread writes over the media and deal with the long erase times of NOR flash blocks[citation needed]. The basic concept behind flash file systems is the following: when the flash store is to be updated, the file system will write a new copy of the changed data to a fresh block, remap the file pointers, then erase the old block later when it has time.
In practice, flash file systems are only used for memory technology devices (MTDs), which are embedded flash memories that do not have a controller. Removable flash memory cards and USB flash drives have built-in controllers to perform wear leveling and error correction so use of a specific flash file system does not add any benefit.[citation needed]
Multiple chips are often arrayed to achieve higher capacities[25] for use in consumer electronic devices such as multimedia players or GPSs. The capacity of flash chips generally follows Moore's Law because they are manufactured with many of the same integrated circuits techniques and equipment.
Consumer flash storage devices typically are advertised with usable sizes expressed as a small integral power of two (2, 4, 8, etc.) and a designation of megabytes or gigabytes (e.g., 512 MB, 8 GB). "MB" and "GB" here (and on the device packaging) are using "decimal prefixes," meaning 1,000,000 bytes and 1,000,000,000 bytes, respectively. This includes SSDs marketed as hard drive replacements, in accordance with traditional hard drives, which also use decimal prefixes. Thus, an SSD marked as "64 GB" is actually at least 64 × 1,0003 bytes (64 GB), or often a bit more. Most users will have slightly less capacity than this available for their files, due to the space taken by file system metadata.
The flash memory chips inside them are sized in strict binary multiples, but the actual total capacity of the chips is not usable at the drive interface. It is considerably larger than the advertised capacity in order to allow for distribution of writes (wear leveling), for sparing, for error correction codes, and for other metadata needed by the device's internal firmware.
In 2005, Toshiba and SanDisk developed a NAND flash chip capable of storing 1 GB of data using multi-level cell (MLC) technology, capable of storing two bits of data per cell. In September 2005, Samsung Electronics announced that it had developed the world’s first 2 GB chip.[26]
In March 2006, Samsung announced flash hard drives with a capacity of 4 GB, essentially the same order of magnitude as smaller laptop hard drives, and in September 2006, Samsung announced an 8 GB chip produced using a 40-nm manufacturing process.[27] In January 2008, Sandisk announced availability of their 16 GB MicroSDHC and 32 GB SDHC Plus cards.[28][29]
More recent flash drives (as of 2012) have much greater capacities, holding 64, 128, and 256 GB.[30] Some of the larger drives, due to their size, can be used for full computer backups.
There are still flash-chips manufactured with capacities under or around 1 MB, e.g., for BIOS-ROMs and embedded applications.
NAND flash memory cards are much faster at reading than writing so it is the maximum read speed that is commonly advertised.
As a chip wears out, its erase/program operations slow down considerably,[citation needed] requiring more retries and bad block remapping. Transferring multiple small files, each smaller than the chip-specific block size, could lead to a much lower rate. Access latency also influences performance, but less so than with their hard drive counterpart.
The speed is sometimes quoted in MB/s (megabytes per second), or as a multiple of that of a legacy single speed CD-ROM, such as 60×, 100× or 150×. Here 1× is equivalent to 150 kB/s. For example, a 100× memory card gives 150 kB/s × 100 = 15,000 kB/s = 14.65 MB/s.
Performance also depends on the quality of memory controllers. Even when the only change to manufacturing is die-shrink, the absence of an appropriate controller can result in degraded speeds.[31]
Serial flash is a small, low-power flash memory that uses a serial interface, typically Serial Peripheral Interface Bus (SPI), for sequential data access. When incorporated into an embedded system, serial flash requires fewer wires on the PCB than parallel flash memories, since it transmits and receives data one bit at a time. This may permit a reduction in board space, power consumption, and total system cost.
There are several reasons why a serial device, with fewer external pins than a parallel device, can significantly reduce overall cost:
- Many ASICs are pad-limited, meaning that the size of the die is constrained by the number of wire bond pads, rather than the complexity and number of gates used for the device logic. Eliminating bond pads thus permits a more compact integrated circuit, on a smaller die; this increases the number of dies that may be fabricated on a wafer, and thus reduces the cost per die.
- Reducing the number of external pins also reduces assembly and packaging costs. A serial device may be packaged in a smaller and simpler package than a parallel device.
- Smaller and lower pin-count packages occupy less PCB area.
- Lower pin-count devices simplify PCB routing.
There are two major SPI flash types. The first type is characterized by small pages and one or more internal SRAM page buffers allowing a complete page to be read to the buffer, partially modified, and then written back (for example, the Atmel AT45 DataFlash™ or the Micron Technology Page Erase NOR Flash). The second type has larger sectors. The smallest sectors typically found in an SPI flash are 4 kB, but they can be as large as 64 kB. Since the SPI flash lacks an internal SRAM buffer, the complete page must be read out and modified before being written back, making it slow to manage. SPI flash is cheaper than DataFlash and is therefore a good choice when the application is code shadowing.
The two types are not easily exchangeable, since they do not have the same pinout, and the command sets are incompatible.
With the increasing speed of modern CPUs, parallel flash devices are often much slower than the memory bus of the computer they are connected to. Conversely, modern SRAM offers access times below 10 ns, while DDR2 SDRAM offers access times below 20 ns. Because of this, it is often desirable to shadow code stored in flash into RAM; that is, the code is copied from flash into RAM before execution, so that the CPU may access it at full speed. Device firmware may be stored in a serial flash device, and then copied into SDRAM or SRAM when the device is powered-up.[32] Using an external serial flash device rather than on-chip flash removes the need for significant process compromise (a process that is good for high-speed logic is generally not good for flash and vice-versa). Once it is decided to read the firmware in as one big block it is common to add compression to allow a smaller flash chip to be used. Typical applications for serial flash include storing firmware for hard drives, Ethernet controllers, DSL modems, wireless network devices, etc.
One more recent application for flash memory is as a replacement for hard disks. Flash memory does not have the mechanical limitations and latencies of hard drives, so a solid-state drive (SSD) is attractive when considering speed, noise, power consumption, and reliability. Flash drives are gaining traction as mobile device secondary storage devices; they are also used as substitutes for hard drives in high-performance desktop computers and some servers with RAID and SAN architectures.
There remain some aspects of flash-based SSDs that make them unattractive. The cost per gigabyte of flash memory remains significantly higher than that of hard disks.[33] Also flash memory has a finite number of P/E cycles, but this seems to be currently under control since warranties on flash-based SSDs are approaching those of current hard drives.[34]
In June 2006, Samsung Electronics released the first flash-memory based PCs, the Q1-SSD and Q30-SSD, both of which used 32 GB SSDs, and were at least initially available only in South Korea.[35]
A solid state drive was offered as an option with the first Macbook Air introduced in 2008, and from 2010 onwards, all Macbook Air laptops shipped with an SSD. Starting in late 2011, as part of Intel's Ultrabook initiative, an increasing number of ultra thin laptops are being shipped with SSDs standard.
There are also hybrid techniques such as hybrid drive and ReadyBoost that attempt to combine the advantages of both technologies, using flash as a high-speed non-volatile cache for files on the disk that are often referenced, but rarely modified, such as application and operating system executable files.
One source states that, in 2008, the flash memory industry includes about US$9.1 billion in production and sales. Other sources put the flash memory market at a size of more than US$20 billion in 2006, accounting for more than eight percent of the overall semiconductor market and more than 34 percent of the total semiconductor memory market.[36]
The aggressive trend of the shrinking process design rule or technology node in NAND flash memory technology effectively accelerates Moore's Law.
Due to its relatively simple structure and high demand for higher capacity, NAND flash memory is the most aggressively scaled technology among electronic devices. The heavy competition among the top few manufacturers only adds to the aggressiveness in shrinking the design rule or process technology node.[13] Current projections show the technology to reach approximately 20 nm by around late 2011. While the expected shrink timeline is a factor of two every three years per original version of Moore's law, this has recently been accelerated in the case of NAND flash to a factor of two every two years.
As the feature size of flash memory cells reach the minimum limit (19 nm as of April 2011[37]), further flash density increases will be driven by greater levels of MLC, possibly 3-D stacking of transistors, and improvements to the manufacturing process. The decrease in endurance and increase in uncorrectable bit error rates that accompany feature size shrinking can be compensated by improved error correction mechanisms.[38] Even with these advances, it may be impossible to economically scale flash to smaller and smaller dimensions. Many promising new technologies (such as FeRAM, MRAM, PMC, PCM, and others) are under investigation and development as possible more scalable replacements for flash.[39]
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- ^ "PSoC Designer(TM) Device Selection Guide – AN2209": "... The PSoC ... utilizes a unique Flash process: SONOS"
- ^ Zitlaw, Cliff. "The Future of NOR Flash Memory". Memory Designline. UBM Media. http://www.eetimes.com/design/memory-design/4215634. Retrieved 3 May 2011.
- ^ Jonathan Thatcher, Fusion-io; Tom Coughlin, Coughlin Associates; Jim Handy, Objective-Analysis; Neal Ekker, Texas Memory Systems (April 2009) (pdf). NAND Flash Solid State Storage for the Enterprise, An In-depth Look at Reliability. Solid State Storage Initiative (SSSI) of the Storage Network Industry Association (SNIA). http://www.snia.org/sites/default/files/SSSI_NAND_Reliability_White_Paper_0.pdf. Retrieved 6 December 2011.
- ^ "Micron Collaborates with Sun Microsystems to Extend Lifespan of Flash-Based Storage, Achieves One Million Write Cycles" (Press release). Micron Technology, Inc.. 17 December 2008. http://investors.micron.com/releasedetail.cfm?ReleaseID=440650.
- ^ "TN-29-17 NAND Flash Design and Use Considerations Introduction". Micron. April 2010. http://download.micron.com/pdf/technotes/nand/tn2917.pdf. Retrieved 29 July 2011.
- ^ a b Kawamatus, Tatsuya. "TECHNOLOGY FOR MANAGING NAND FLASH". Hagiwara sys-com co., LTD. http://techon.nikkeibp.co.jp/NEA/solutions/0808002.pdf. Retrieved 1 August 2011.
- ^ Kim, Jesung; Kim, John Min; Noh, Sam H.; Min, Sang Lyul; Cho, Yookun (2002-05). "A Space-Efficient Flash Translation Layer for CompactFlash Systems". Proceedings of the IEEE 48 (2): pp. 366–375. http://ieeexplore.ieee.org/iel5/30/21778/01010143.pdf?tp=&isnumber=&arnumber=1010143. Retrieved 15 August 2008.
- ^ TN-29-07: Small-Block vs. Large-Block NAND flash Devices Explains 512+16 and 2048+64-byte blocks
- ^ AN10860 LPC313x NAND flash data and bad block management Explains 4096+128-byte blocks.
- ^ Smith, Lance L. (18 August 2009). "NAND Flash Solid State Storage Performance and Capability – an In-depth Look". SNIA. http://www.flashmemorysummit.com/English/Collaterals/Proceedings/2009/20090812_T1B_Smith.pdf. Retrieved 17 June 2010.
- ^ "Samsung ECC algorithm" (PDF). Samsung. 2008-06. http://www.elnec.com/sw/samsung_ecc_algorithm_for_256b.pdf. Retrieved 15 August 2008.
- ^ "Open NAND Flash Interface Specification" (PDF). Open NAND Flash Interface. 28 December 2006. http://onfi.org/wp-content/uploads/2009/02/onfi_1_0_gold.pdf. Retrieved 31 July 2010.
- ^ A list of ONFi members is available at http://onfi.org/membership/.
- ^ "Dell, Intel And Microsoft Join Forces To Increase Adoption Of NAND-Based Flash Memory In PC Platforms". REDMOND, Wash: Intel. 30 May 2007. http://www.intel.com/pressroom/archive/releases/20070530corp.htm. Retrieved 30 November 2008. [dead link]
- ^ See pages 5–7 of Toshiba's "NAND Applications Design Guide" under External links.
- ^ Pavan, Paolo; Bez, Roberto; Olivo, Piero; Zononi, Enrico (1997). "Flash Memory Cells – An Overview". Proceedings of the IEEE 85 (8): pp. 1248–1271. 1997-08. DOI:10.1109/5.622505. http://ieeexplore.ieee.org/iel3/5/13533/00622505.pdf?tp=&isnumber=&arnumber=622505. Retrieved 15 August 2008.
- ^ "NAND Evolution and its Effects on Solid State Drive Useable Life". Western Digital. 2009. http://www.wdc.com/WDProducts/SSD/whitepapers/en/NAND_Evolution_0812.pdf. Retrieved 22 April 2012.
- ^ "Flash vs DRAM follow-up: chip stacking". The Daily Circuit. 22 April 2012. http://www.dailycircuitry.com/2012/04/as-follow-up-to-our-flash-vs-dram.html. Retrieved 22 April 2012.
- ^ Shilov, Anton (12 September 2005). "Samsung Unveils 2GB Flash Memory Chip". X-bit labs. http://www.xbitlabs.com/news/memory/display/20050912212649.html. Retrieved 30 November 2008.
- ^ Gruener, Wolfgang (11 September 2006). "Samsung announces 40-nm Flash, predicts 20 nm devices". TG Daily. http://www.tgdaily.com/content/view/28504/135/. Retrieved 30 November 2008.
- ^ 12 GB MicroSDHC
- ^ 32 GB SDHC Plus
- ^ http://www.pcworld.com/businesscenter/article/225370/look_out_for_the_256gb_thumb_drive_and_the_128gb_tablet.html; http://techcrunch.com/2009/07/20/kingston-outs-the-first-256gb-flash-drive/ 20 July 2009, Kingston DataTraveler 300 is 256 GB.
- ^ Samsung Confirms 32nm Flash Problems, Working on New SSD Controller
- ^ Many serial flash devices implement a bulk read mode and incorporate an internal address counter, so that it is trivial to configure them to transfer their entire contents to RAM on power-up. When clocked at 50 MHz, for example, a serial flash could transfer a 64 Mbit firmware image in less than two seconds.
- ^ Lyth0s (17 March 2011). "SSD vs. HDD". elitepcbuilding.com. http://elitepcbuilding.com/ssd-vs-hdd. Retrieved 11 July 2011.
- ^ "Flash Solid State Disks – Inferior Technology or Closet Superstar?". STORAGEsearch. http://www.storagesearch.com/bitmicro-art1.html. Retrieved 30 November 2008.
- ^ "Samsung Electronics Launches the World’s First PCs with NAND Flash-based Solid State Disk". Press Release. Samsung. 24 May 2006. http://www.samsung.com/he/presscenter/pressrelease/pressrelease_20060524_0000257996.asp. Retrieved 30 November 2008.
- ^ Yinug, Christopher Falan (July 2007). "The Rise of the Flash Memory Market: Its Impact on Firm Behavior and Global Semiconductor Trade Patterns" (PDF). Journal of International Commerce and Economics. Archived from the original on 29 May 2008. http://web.archive.org/web/20080529180622/http://www.usitc.gov/journal/Final_falan_article1.pdf. Retrieved 19 April 2008.
- ^ Curtis Ray, Austin (21 April 2011). "SanDisk Announces 19nm Memory Chip". Maximum PC. http://www.maximumpc.com/article/news/sandisk_announces_19nm_memory_chip. Retrieved 21 April 2011.
- ^ Lal Shimpi, Anand (2 December 2010). "Micron's ClearNAND: 25nm + ECC, Combats Increasing Error Rates". Anandtech. http://www.anandtech.com/show/4043/micron-announces-clearnand-25nm-with-ecc. Retrieved 2 December 2010.
- ^ Kim, Kinam; Koh, Gwan-Hyeob (16 May 2004). Future Memory Technology including Emerging New Memories. Serbia and Montenegro: Proceedings of the 24th International Conference on Microelectronics (published 2004-05). pp. 377–384. http://ieeexplore.ieee.org/iel5/9193/29143/01314646.pdf?tp=&isnumber=&arnumber=1314646. Retrieved 15 August 2008.
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