Sun UltraSPARC II Microprocessor

SPARC (from Scalable Processor Architecture) is a RISC instruction set architecture (ISA) developed by Sun Microsystems and introduced in mid-1987.

SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC architecture, manage SPARC trademarks, and provide conformance testing. Implementations of the original 32-bit SPARC architecture were initially designed and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 family of processors. Later, SPARC processors were used in SMP servers produced by Sun Microsystems, Solbourne and Fujitsu, among others, and designed for 64-bit operation.

SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments, Atmel, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.

In March 2006, the complete design of Sun Microsystems' UltraSPARC T1 microprocessor was released-in open-source form at OpenSPARC.net and named the OpenSPARC T1. In 2007, the design of Sun's UltraSPARC T2 microprocessor was also released in open-source form, as OpenSPARC T2.^[1]

The most recent commercial iterations of the SPARC processor design are the Fujitsu Laboratories Ltd.'s "Venus" 128 GFLOP SPARC64 VIIIfx introduced June 2009, which is used in the 8 petaFLOPS Japanese supercomputer "K computer", and the SPARC T4 introduced by Oracle Corporation in September 2011; both are 8 core devices running at 2.0GHz, and over 2.5GHz respectively.

Features[link]

The SPARC architecture was heavily influenced by the earlier RISC designs including the RISC I and II from the University of California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 160 general purpose registers. At any point, only 32 of them are immediately visible to software - 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only 7 of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.

The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from 3 to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only 3 to reduce context switching time, or to implement some number between them. Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The architecture has gone through several revisions. It gained hardware multiply and divide functionality in Version 8.^[2][3] 64-bit (addressing and data) were added to the version 9 SPARC specification published in 1994.^[4]

In SPARC Version 8, the floating point register file has 16 double precision registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. SPARC Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers.

Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load/store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.

History[link]

There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended precision" floating-point arithmetic to 128-bit "quad-precision" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.

SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments.

In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".

In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions (such as CMT, hyperprivileged, VIS 1, and VIS 2) present in Sun's UltraSPARC processors starting with the UltraSPARC T1 implementation. UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification.

In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.

The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

The SPARC architecture has been licensed to many companies who have developed and fabricated implementations such as:

• Afara Websystems
• Bipolar Integrated Technology (BIT)
• C-Cube
• Cypress Semiconductor
• Elbrus
• Fujitsu and Fujitsu Microelectronics
• HAL Computer Systems
• Hyundai
• LSI Logic
• Magnum Semiconductor
• Meiko Scientific
• Metaflow Technologies
• Prisma
• Ross Technology
• Parsé Semiconductor Co.
• Scientific Atlanta
• Solbourne Computer
• Weitek

SPARC microprocessor specifications[link]

This table contains specifications for certain SPARC processors: frequency (megahertz), architecture version, release year, number of threads (threads per core multiplied by the number of cores), fabrication process (micrometers), number of transistors (millions), die size (square millimetres), number of I/O pins, dissipated power (watts), voltage, and cache sizes—data, instruction, L2 and L3 (kibibytes).

Notes:

Operating system support[link]

SPARC machines have generally used Sun's SunOS, Solaris or OpenSolaris, but other operating systems such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux have also been used.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture,^[16] but it was later cancelled.

Open source implementations[link]

Three fully open source implementations of the SPARC architecture exist:

• LEON, a 32-bit, SPARC Version 8 implementation, designed especially for space use. Source code is written in VHDL, and licensed under the GPL.
• OpenSPARC T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary software license agreement.
  • S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC v9 core capable of 4 way SMT. Like the T1, the source code is licensed under the GPL.
• OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement.

A fully open source simulator for the SPARC architecture also exists:

• RAMP Gold, a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of Systemverilog, and licensed under the BSD licenses.

Supercomputers[link]

As of June 2011, only two supercomputers (#1 and #73) using SPARC microprocessors are included in the world's top 500 fastest supercomputers according to the TOP500 list. ^[17]

Fujitsu's K computer ranked #1 in Top500 - June 2011 and Nov 2011 lists.^[17] It combines 88,128 SPARC64 VIIIfx CPUs, each with eight cores, for a total of 705,024 cores—almost twice as many as any other system in the TOP500. The K Computer is more powerful than the next five systems on the list combined, and has the highest performance-to-power ratio of any current supercomputer system. It also ranked #6 in Green500 - June 2011 list, with a score of 824.56 MFLOPS/W.^[18]

Tianhe-1A (currently #2) has a number of nodes with FeiTeng-1000 SPARC-based processors developed in China (based on OpenSPARC). However, those processors did not contribute to the LINPACK score.^[19][20]

On Dec. 2, 2010, Oracle unveiled the SPARC SuperCluster with T3-2, T3-4 and M5000 servers.^[21] The configuration with T3-4 servers was claimed to surpass the HP Integrity Superdome and the IBM Power 780 server, reaching speeds of 30,249,688 tpmC.^[22]

See also[link]

• ERC32 – based on SPARC V7 specification
• FeiTeng-1000 – A Chinese eight core Sparc based processor
• MCST-4R – A Russian quad-core microprocessor based on SPARC V9 specification
• OpenSPARC – an open source project based on the UltraSPARC T1 design
• Rock processor – A multicore and multithread microprocessor with an emphasis on floating-point performance
• Ross Technology, Inc. – A SPARC microprocessor developer during the 1980s and 1990s
• Sparcle – modified SPARC with multiprocessing support used by the MIT Alewife project
• UltraSPARC T1 – Sun's first multicore and multithread CPU (code-named "Niagara")
• UltraSPARC T2 – The successor to T1
• SPARC T3 – The successor to UltraSPARC T2

References[link]

External links[link]

• SPARC International, Inc.
• SPARC International list of SPARC processors
• SPARC International Technical Documents
• UltraSPARC Architecture 2005 specification - a SPARC architecture specification extended with CMT, hyperprivileged mode, VIS 1, VIS 2, and so forth for UltraSPARC processors
• UltraSPARC Architecture 2007 specification - an updated SPARC architecture specification for UltraSPARC processors shipping 2007+
• UltraSPARC Processors
• SPARC processor images and descriptions
• The Rough Guide to MBus Modules (SuperSPARC, hyperSPARC)
• SPARC at the Open Directory Project

The 100: A Ranking of the Most Influential Persons in History is a 1978 book by Michael H. Hart, reprinted in 1992 with revisions. It is a ranking of the 100 people who, according to Hart, most influenced human history.^[1]

The first person on Hart's list is the Prophet of Islam Muhammad.^[2] Hart asserted that Muhammad was "supremely successful" in both the religious and secular realms. He also believed that Muhammad's role in the development of Islam was far more influential than Jesus' collaboration in the development of Christianity. He attributes the development of Christianity to St. Paul, who played a pivotal role in its dissemination."^[3]

The 1992 revisions included the demotion of figures associated with Communism, such as Vladimir Lenin and Mao Zedong, and the introduction of Mikhail Gorbachev. Hart took sides in the Shakespearean authorship issue and substituted Edward de Vere, 17th Earl of Oxford for William Shakespeare. Hart also substituted Niels Bohr and Henri Becquerel with Ernest Rutherford, thus correcting an error in the first edition. Henry Ford was also promoted from the "Honorary Mentions" list, replacing Pablo Picasso. Finally, some of the rankings were re-ordered, although no one listed in the top ten changed position.

Hart wrote another book in 1999, entitled A View from the Year 3000,^[4] voiced in the perspective of a person from that future year and ranking the most influential people in history. Roughly half of those entries are fictional people from 2000–3000, but the remainder are actual people. These were taken mostly from the 1992 edition, with some re-ranking of order.

Hart's Top 10 (from the 1992 edition)[link]

Rank	Name	Time Frame	Image	Occupation	Influence
1	Muhammad	c. 570–632		Secular and religious leader	The central human figure of Islam, regarded by Muslims as a prophet of God and the last messenger. Active as a social reformer, diplomat, merchant, philosopher, orator, legislator, military leader, humanitarian, philanthropist.
2	Isaac Newton	1643–1727		Scientist	English physicist, mathematician, astronomer, natural philosopher, alchemist, and theologian. His law of universal gravitation and three laws of motion laid the groundwork for classical mechanics.
3	Jesus Christ	7–2 BC – 26–36 AD		Spiritual leader	The central figure of Christianity, revered by Christians as the Son of God and the incarnation of God.
4	Buddha	563–483 BC		Spiritual leader	Spiritual teacher and philosopher from ancient India. Founder of Buddhism and is also considered an Gautama Buddha in Hinduism.
5	Confucius	551–479 BC		Philosopher	Chinese thinker and social philosopher, whose teachings and philosophy have deeply influenced Chinese, Korean, Japanese, Vietnamese and Indonesian thought and life. Founded Confucianism, and influenced Neo-Confucianism and New Confucianism.
6	St. Paul	5–67 AD		Christian apostle	One of the most notable of early Christian missionaries, credited with proselytizing and spreading Christianity outside of Palestine (mainly to the Romans) and author of numerous letters of the New Testament of the Bible.
7	Cài Lún	50–121 AD		Political official in imperial China	Widely regarded as the inventor of paper and the papermaking process.
8	Johannes Gutenberg	1398–1468		Inventor	German printer who invented the mechanical printing press.
9	Christopher Columbus	1451–1506	70px	Explorer	Italian navigator, colonizer and explorer whose voyages led to general European awareness of the American continents.
10	Albert Einstein	1879–1955		Scientist	German theoretical physicist, best known for his theory of relativity and specifically mass–energy equivalence, expressed by the equation E = mc2.

See also[link]

• Time 100

References[link]

1. ^ Michael H. Hart The 100: A Ranking of the Most Influential Persons in History. first published in 1978, reprinted with minor revisions 1992. ISBN 978-0-8065-1068-2
2. ^ The 100: A Ranking of the Most Influential Persons in History^{[dead link]}
3. ^ Michael H. Hart, "The 100: A Ranking of the Most Influential Persons in History", Citadel Publishing, 2000, ISBN 978-0-8065-1350-8
4. ^ Michael H. Hart. A view from the year 3000: a ranking of the 100 most influential persons of all time; first published in 1999

External links[link]

• Religious Affiliation of History's 100 Most Influential People