QorIQ ( /ˈkɔr.aɪ.kjuː/) is a brand of Power Architecture-based communications microprocessors from Freescale. It is the evolutionary step from the PowerQUICC platform and will be built around one or more Power Architecture e500mc cores and come in five different product platforms, P1, P2, P3, P4 and P5, segmented by performance and functionality. The platform keeps software compatibility with older PowerPC products such as the PowerQUICC platform.

The QorIQ brand and the P1, P2 and P4 product families were announced in June 2008. Details of P3 and P5 products were announced in 2010.

QorIQ P Series processors will be manufactured on a 45 nm fabrication process and was available in the end of 2008 (P1 and P2), mid 2009 (P4) and 2010 (P5). The roadmap stretched beyond the 28 nm process, and all are pushing a very aggressive power envelope target, capping at 30 W.

P Series[link]

The QorIQ P Series processors are based on Power Architecture e500 or e5500 cores. The P10xx and P20xx series are based on the e500v2 core, P30xx and P40xx on the e500mc core, and P50xx on the e5500 core. Features include 32/32 kB data/instruction L1 cache, 36-bit physical memory addressing [appended to the top of the virtual address in the process context, each process is still 32bit], a double precision floating point unit is present on some cores (not all) and support for virtualization through a hypervisor layer is present in products featuring the e500mc or the e5500. The dual and multi-core devices supports both symmetric and asymmetric multiprocessing, and can run multiple operating systems in parallel.

P1[link]

The P1 series is tailored for gateways, Ethernet switches, wireless LAN access points, and general-purpose control applications. It is the entry level platform, ranging from 400 to 800 MHz devices. It is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms. The chips include among other integrated functionality, Gigabit Ethernet controllers, two USB 2.0 controllers, a security engine, a 32-bit DDR2 and DDR3 memory controller with ECC support, dual four-channel DMA controllers, a SD/MMC host controller and high speed interfaces which can be configured as SerDes lanes, PCIe and SGMII interfaces. The chip is packaged in 689-pin packages which are pin compatible with the P2 family processors.

• P1011 – Includes one 800 MHz e500 core, 256 kB L2 cache, four SerDes lanes, three Gbit Ethernet controllers and a TDM engine for legacy phone applications.
• P1020 – includes two 800 MHz e500 cores, 256 kB shared L2 cache, four SerDes lanes, three Gbit Ethernet controllers and a TDM engine.
• Freescale announces pin-compatible, power-efficient series in new QorIQ communications platforms – Freescale.com
• P1 Series Single- and Dual-Core Communications Processors – Freescale.com

P2[link]

The P2 series is designed for a wide variety of applications in the networking, telecom, military and industrial markets. It will be available in special high quality parts, with junction tolerances from -40 to 125 °C, especially suited for demanding out doors environments. It is the mid-level platform, with devices ranging from 800 MHz up to 1.2 GHz. It is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms. The chips include, among other integrated functionality, a 512 kB L2 cache, a security engine, three Gigabit Ethernet controllers, a USB 2.0 controller, a 64-bit DDR2 and DDR3 memory controller with ECC support, dual four-channel DMA controllers, a SD/MMC host controller and high speed SerDes lanes which can be configured as three PCIe interfaces, two RapidIO interfaces and two SGMII interfaces. The chips are packaged in 689-pin packages which are pin compatible with the P1 family processors.

• P2010 – Includes one 1.2 GHz core
• P2020 – Includes two 1.2 GHz cores, with shared L2 cache
• Freescale announces pin-compatible, power-efficient series in new QorIQ communications platforms – Freescale.com
• P2 Series Single- and dual-core communications processors – Freescale.com
• P2040
• P2041

P3[link]

The P3 series is a mid performance networking platform, designed for switching and routing. The P3 family offers a multi-core platform, with support for up to four Power Architecture e500mc cores at frequencies up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches, memory controller, multiple I/O-devices such as DUART, GPIO and USB 2.0, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet, RapidIO or PCIe interfaces.[1]

The P3 family processors share the same physical package with, and are also software backwards compatible with, P4 and P5. The P3 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions, RAID, security, cryptography and RapidIO.

The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications.

• P3041 - Quad 1.5 GHz cores, 128 kB L2 cache per core, single 1.3 GHz 64-bit DDR3 controller. Manufactured on a 45 nm process operating in a 12W envelope.

P4[link]

The P4 series is a high performance networking platform, designed for backbone networking and enterprise level switching and routing. The P4 family offers an extreme multi-core platform, with support for up to eight Power Architecture e500mc cores at frequencies up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches, memory controllers, multiple I/O-devices such as DUART, GPIO and USB 2.0, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet, RapidIO or PCIe interfaces.

The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications.

• P4080 – Includes eight e500mc cores, each with 32/32kB instruction/data L1 caches and a 128 kB L2 cache. The chip has dual 1 MB L3 caches, each connected to a 64-bit DDR2/DDR3 memory controller. The chip contains a security and encryption module, capable of packet parsing and classification, and acceleration of encryption and regexp pattern matching. The chip can be configured with up to eight Gigabit and two 10 Gigabit Ethernet controllers, three 5 GHz PCIe ports and two RapidIO interfaces. It also has various other peripheral connectivity such as two USB2 controllers. It is designed to operate below 30 W at 1.5 GHz. The processor is manufactured on a 45 nm SOI process and begun sampling to customers in August 2009.^[1]
• Eight-core microprocessor from Freescale redefines state-of-the-art for embedded multicore processing – Freescale.com
• P4 Series P4080 multicore processor – Freescale.com

To help software developers and system designers get started with the QorIQ P4080, Freescale worked with Virtutech to create a virtual platform for the P4080 that can be used prior to silicon availability to develop, test, and debug software for the chip. Currently, the simulator is only for the P4080, not the other chips announced in 2008.^[2]

Because of its complete set of network engines, this processor can be used for telecommunication systems (LTE eNodeB, EPC, WCDMA, BTS), so Freescale and 6WIND ported 6WIND's packet processing software to the P4080.

P5[link]

The P5 series is based on the high performance 64-bit e5500 core scaling up to 2.5 GHz and allowing numerous auxiliary application processing units as well as multi core operation via the CoreNet fabric. The P5 series processors share the same physical package and a is also software backwards compatible with P3 and P4. The P5 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions, RAID, security, cryptography and RapidIO.

Introduced in June 2010, samples will be available late 2010 and full production is expected in 2011.

Applications rage from high end networking control plane infrastructure, high end storage networking and complex military and industrial devices.

• P5010 - Single e5500 2.2 GHz core, 1 MB L3 cache, single 1.333&nbsplGHz DDR3 controller, manufactured on a 45 nm process and operating in a 30W envelope.
• P5020 - Dual e5500 2.2 GHz cores, dual 1 MB L3 caches, dual 1.333&nbsplGHz DDR3 controllers, manufactured on a 45 nm process and operating in a 30W envelope.
• P5021 - Dual e5500 2.4 GHz cores, 1.6 GHz DDR3/3L. Sampling since March 2012; production expected in 4Q12.
• P5040 - Quad e5500 2.4 GHz cores, 1.6 GHz DDR3/3L. Sampling since March 2012; production expected in 4Q12.

Qonverge[link]

In February 2011 Freescale introduced the QorIQ Qonverge platform which is a series of combined CPU and DSP SoC processors targeted wireless infrastructure applications.^[3] The PSC913x family chips uses an e500 core based CPU and StarCore SC3850 DSPs will be available in 2011, and is manufactured on a 45 nm process, with 28 nm parts on the roadmap for more demanding applications.

AMP Series[link]

The QorIQ Advanced Multiprocessing, AMP Series, processors are all based on the multithreaded 64-bit e6500 core with integrated AltiVec SIMD processing units. Products will range from single core versions up to parts with 12 cores or more with frequencies ranging all the way up to 2.5 GHz. The processes will be sectioned into five classes according to performance and features, named T1 through T5, and will be manufactured in a 28 nm process beginning in 2012.^[4]

T4[link]

• T4240 – The first product announced and will incorporate twelve e6500 dual-threaded cores, three memory controllers and various other accelerators.^[5]

System Design[link]

Networking, IT and telecommunication systems[link]

The QorIQ products bring some new challenges in order to design some control planes of telecommunication systems and their data plane. For instance, when 4 or 8 cores are used, such as the P4080, in order to achieve millions of Packet Processing per seconds, the system does not scale with regular software stack because so many cores require a different system design. In order to restore simplicity and still get the highest level of performance, the telecommunication systems are based on a segregation of the cores. Some cores are used for the control plane while some others are used for a re-designed data plane based on a Fast Path.

Freescale has partnered with networking company 6WIND to provide software developers with a high-performance commercial packet processing solution for the QorIQ platform.^[6]

See also[link]

• Power Architecture
• PowerQUICC
• PowerPC e500

References[link]

External links[link]

• Freescale QorIQ communications platforms signal a new way forward for embedded multicore technology - Freescale.com
• Freescale's QorIQ website
• QorIQ moves Power architecture to multicore – EDN.com
• MontaVista: multicore Linux support for Freescale QorIQ P4080 – EmbeddedControlEurope.com
• QorIQ 45-nm communications MPUs feature dual cores, low power – ElectronicProducts.com
• Virtutech Enables Multi-Core Development Ecosystem for Freescale Power Architecture QorIQ P4080 Processor – TradingMarkets.com
• MontaVista Provides First No-Cost Evaluation of Commercial Linux for Freescale QorIQ P4080 Multicore Processor – Money.AOL.com
• Halfhill, Tom R. (7 July 2008). "Freescale's Multicore Makeover". Microprocessor Report.