Caption contest: Mars attacks!
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FPGA-based instrumentation withstands chill in deep space
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Interfacing QDR-II+ Synchronous SRAM with high-speed FPGAs, part 1
Networking memories--High access rates for packet-header processing—Part II
Book excerpt: SRAM and SDRAM controllers for FPGAs, part 3
Networking memories for buffering applications—Part I
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Book excerpt: SRAM and SDRAM controllers for FPGAs, part 2
Optimizing PCIe SSD performance
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Book excerpt: SRAM and SDRAM controllers for FPGAs, part 1
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The forgotten SoC verification team
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Surge protection—Stop fried electronics
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Breaking through the embedded memory bottleneck, part 2
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Network switch device equipment balances performance, cost and power in the cloud
Breaking through the embedded memory bottleneck, part 1
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Diagnostic and repair tools for embedded memory boost SoC yields
FRAMs as alternatives to flash memory in embedded designs
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The Memory Designline is edited by Kristin Lewotsky. Please contact Kristin at