SDRAM latency refers to the delays incurred when a
computer tries to access
data in
SDRAM. SDRAM latency is often measured in memory bus
clock cycles. Because a modern
CPU is much faster than SDRAM, the CPU has to wait for a relatively long time for a memory access to complete before it can process the data. SDRAM latency contributes to total
memory latency, which causes a significant
bottleneck for system performance in modern computers.
SDRAM access
SDRAM is notationally organized into a grid like pattern, with "rows" and "columns". The data stored in SDRAM comes in blocks, defined by the coordinates of the row and column of the specific information. The steps for the memory controller to access data in SDRAM follow in order:
# First, the SDRAM is in an idle state.
# The controller issues the "active" command. It activates a certain row, as indicated by the address lines, in the SDRAM chip for accessing. This command typically takes a few clock cycles.
# After the delay, column address and either "read" or "write" command is issued. Typically the read or write command can be repeated every clock cycle for different column addresses (or a burst mode read can be performed). The read data isn't however available until a few clock cycles later, because the memory is pipelined.
# When an access is requested to another row, the current row has to be deactivated by issuing the "precharge" command. The precharge command takes a few clock cycles before a new "active" command can be issued.
SDRAM access has four main measurements (quantified in FSB clock cycles) important in defining the SDRAM latency in a given computer (the 't' prefixes are for 'time'):
;tCAS
:The number of clock cycles needed to access a certain column of data in SDRAM. CAS latency, or simply CAS, is known as Column Address Strobe time, sometimes referred to as tCL.
;tRCD (RAS to CAS Delay)
:The number of clock cycles needed between a row address strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. tRCD stands for Row address to Column address Delay time.
;tRP (RAS Precharge)
:The number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. It stands for Row Precharge time.
;tRAS (Row Active Time)
:The minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. It's known as active to precharge delay. According to Mushkin, in practice for DDR SDRAM, this should be set to at least tRCD + tCAS + 2 to allow enough time for data to be streamed out. . It stands for Row Address Strobe time.
Pictorially the timings operate as follows:
{|class=wikitable style=text-align:center
|+ SDRAM access timing
!colspan=3| Row access !!colspan=6| Column accesses !!colspan=3| Precharge
|-
|width=30| ||width=30| ||width=30| ||width=30| ||width=30| ||width=30| ||width=30| ||width=30| ||width=30| ||width=30| ||width=30| ||width=30|
|-
|rowspan=4 colspan=3|tRCD ||colspan=3|tCAS (R) ||colspan=3| ||rowspan=5 colspan=3|tRP
|-
| ||colspan=5|tWR (Write)
|-
|colspan=2| ||colspan=3|tCAS (R)||
|-
|colspan=3| ||colspan=3|tCAS (R)
|-
|colspan=9|tRAS
|-
| || || || || || || || || || || ||
|}
Initially, the row address is sent to the DRAM. After tRCD, the row is open and may be accessed. Because this is an SDRAM, multiple column access can be in progress at once. Each read takes time tCAS. When we are done accessing the column, we precharge the SDRAM, which returns us to the starting state after time tRP.
Two other time limits that must also be maintained are tRAS, the time for the refresh of the row to complete before it may be closed again, and tWR, the time that must elapse after the last write before the row may be closed.
Measurements
As with almost all latency measurement, lower latency results in better performance. RAM speeds are given by the four numbers above, in the format "tCAS-tRCD-tRP-tRAS". So, for example, latency values given as 2.5-3-3-8 would indicate tCAS=2.5, tRCD=3, tRP=3, tRAS=8. (Note that 0.5 values of latency (such as 2.5) are only possible in
double data rate (DDR) RAM, where two parts of each clock cycle are used)
Most computer users don't need to worry about setting the SDRAM latency because the computer can handle the auto-adjustment to RAM timing based on the Serial Presence Detect (SPD) ROM inside the RAM packaging that defines the four timing values, decided by the RAM manufacturer. Although the SDRAM latency timing can often be adjusted manually, using lower latency settings than the module's rating (overclocking) may cause a computer to crash or fail to boot.
Regardless of the said risk, more intrepid computer users have found that the manufacturer may not attempt to set the best settings in the SPD ROM because the timings of mainstream modules don't affect their sales; as timings are rarely if ever a selling point for pre-built computers. They use programs such as Memset or AMD Overdrive to reduce the default latencies to the least that the modules can practically function at. For example, a one GB module of 400MHz Nanya SD DDR2 RAM is set at 6-6-6-18 with a command rate of 2T, but can support 6-5-4-11 with a command rate of 1T and function without instability.
See also
Dynamic random access memory
Memory latency
External links
Category:SDRAM
Category:Computer memory
