In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory (DRAM) with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s. DDR3 SDRAM is not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, and other factors.

DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance.

The primary benefit of DDR3 SDRAM over its immediate predecessor, DDR2 SDRAM, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates. With two transfers per cycle of a quadrupled clock, a 64-bit wide DDR3 module may achieve a transfer rate of up to 64 times the memory clock speed in megabytes per second (MB/s). With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s. In addition, the DDR3 standard permits chip capacities of up to 8 gigabits.

Overview

DDR3 memory provides a reduction in power consumption of 30% compared to DDR2 modules due to DDR3's 1.5 V supply voltage, compared to DDR2's 1.8 V or DDR's 2.5 V. The 1.5 V supply voltage works well with the 90 nanometer fabrication technology used in the original DDR3 chips. Some manufacturers further propose using "dual-gate" transistors to reduce leakage of current.

According to JEDEC the maximum recommended voltage is 1.575 volts and should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission critical devices. In addition, JEDEC states that memory modules must withstand up to 1.975 volts before incurring permanent damage, although they are not required to function correctly at that level.

Two low voltage DDR3 standards have been introduced by JEDEC. The DDR3L standard operates with a default voltage of 1.35V, using at least 15% less power than standard voltage (1.5V) DDR3. Modules with DDR3L are labeled ’’PC3L’’, and examples include DDR3L‐800, DDR3L‐1066, DDR3L‐1333, and DDR3L‐1600. The DDR3U standard operates with a default voltage of 1.25V, and modules are labelled ’’PC3U’’.

The main benefit of DDR3 comes from the higher bandwidth made possible by DDR3's 8-burst-deep prefetch buffer, in contrast to DDR2's 4-burst-deep or DDR's 2-burst-deep prefetch buffer.

DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges of a 400–1066 MHz I/O clock. Sometimes, a vendor may misleadingly advertise the I/O clock rate by labeling the MT/s as MHz. The MT/s is normally twice that of MHz by double sampling, one on the rising clock edge, and the other, on the falling. In comparison, DDR2's current range of data transfer rates is 400–1066 MT/s using a 200–533 MHz I/O clock, and DDR's range is 200–400 MT/s based on a 100–200 MHz I/O clock. High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between framebuffers is required.

DDR3 does use the same electric signaling standard as DDR and DDR2, Stub Series Terminated Logic, albeit at different timings and voltages. Specifically DDR3 uses SSTL_15..

DDR3 prototypes were announced in early 2005. Products in the form of motherboards appeared on the market in June 2007 based on Intel's P35 "Bearlake" chipset with DIMMs at bandwidths up to DDR3-1600 (PC3-12800). The Intel Core i7, released in November 2008, connects directly to memory rather than via a chipset. The Core i7 supports only DDR3. AMD's first socket AM3 Phenom II X4 processors, released in February 2009, were their first to support DDR3.

DDR3 DIMMs have 240 pins and are electrically incompatible with DDR2. The two are prevented from being accidentally interchanged by different key notch positions on the DIMMs. DDR3 SO-DIMMs have 204 pins.

GDDR3 memory, sometimes incorrectly referred to as "DDR3" due to its similar name, is an entirely different technology, as it is designed for use in graphics cards and technologically based on DDR2 SDRAM.

Latencies

While the typical latencies for a JEDEC DDR2 device were 5-5-5-15, some standard latencies for JEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 and 8-8-8-24 for DDR3-1333.

DDR3 latencies are numerically higher because the I/O bus clock cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies (around 10 ns). There is some improvement because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3.

As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide with the Intel Core i7 release. CAS latency of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS latency of 7 at 667 MHz (DDR3-1333) is 10.5 ns.

(CAS / Frequency (MHz)) × 1000 = X ns

Example:

(7 / 667) × 1000 = 10.4948 ns

Extensions

Intel Corporation officially introduced the eXtreme Memory Profile (XMP) Specification on March 23, 2007 to enable enthusiast performance extensions to the traditional JEDEC SPD specifications for DDR3 SDRAM.

Modules

JEDEC standard modules

{|class="wikitable" style="text-align:center" !Standard name   !Memory clock (MHz) !Cycle time (ns) !I/O bus clock (MHz) !Data rate (MT/s) !Module name   !Peak transfer rate (MB/s) !Timings (CL-tRCD-tRP) !CAS latency (ns) |- | DDR3-800DDDR3-800E || 100 || 10 || 400 || 800 || PC3-6400 || 6400 || 5-5-56-6-6 || 15   |- | DDR3-1066EDDR3-1066FDDR3-1066G || 133⅓ || || 533⅓ || 1066⅔ || PC3-8500 || 8533⅓ || 6-6-67-7-78-8-8 || 15   |- | DDR3-1333F*DDR3-1333GDDR3-1333HDDR3-1333J* || 166⅔ || 6 || 666⅔ || 1333⅓ || PC3-10600 || 10666⅔ || 7-7-78-8-89-9-910-10-10 || 12  15   |- | DDR3-1600G*DDR3-1600HDDR3-1600JDDR3-1600K || 200 || 5 || 800 || 1600 || PC3-12800 || 12800 || 8-8-89-9-910-10-1011-11-11 || 10   |- | DDR3-1866J*DDR3-1866KDDR3-1866LDDR3-1866M* || 233⅓ || || 933⅓ || 1866⅔ || PC3-14900 || 14933⅓ || 10-10-1011-11-1112-12-1213-13-13 ||    |- | DDR3-2133K*DDR3-2133LDDR3-2133MDDR3-2133N* || 266⅔ || || 1066⅔ || 2133⅓ || PC3-17000 || 17066⅔ || 11-11-1112-12-1213-13-1314-14-14 ||    |} * optional

CL - Clock cycles between sending a column address to the memory and the beginning of the data in response

tRCD - Clock cycles between row activate and reads/writes

tRP - Clock cycles between row precharge and activate

Fractional frequencies are normally rounded down, but rounding up to -667 is common due to superstition about the number 666.

Note: All above listed are specified by JEDEC as JESD79-3D. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, the highest reported speed reached was equivalent to DDR3-2544 as of May 2010.

DDR3-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

In addition to bandwidth and capacity variants, modules can #Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E. #Be "registered", which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a register, at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC3-6400R is a registered PC3-6400 module, PC3-6400R ECC is the same module but with additional ECC. #Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.

Feature summary

; DDR3 SDRAM components

Introduction of asynchronous RESET pin

Support of system-level flight-time compensation

On-DIMM mirror-friendly DRAM pinout

Introduction of CWL (CAS write latency) per clock bin

On-die I/O calibration engine

READ and WRITE calibration

; DDR3 modules

Fly-by command/address/control bus with on-DIMM termination

High-precision calibration resistors

Are not backwards compatible—DDR3 modules do not fit into DDR2 sockets; forcing them can damage the DIMM and/or the motherboard

; Technological advantages compared to DDR2

Higher bandwidth performance, up to 2133 MT/s standardized

Slightly improved latencies as measured in nanoseconds

Higher performance at low power (longer battery life in laptops)

Enhanced low-power features

Development and market penetration

In May 2005, Desi Rhoden, chairman of the JEDEC Committee responsible for creating the DDR3 standard, stated that DDR3 had been under development for "about 3 years". DDR3 was launched in 2007, however sales were not expected to overtake DDR2 until the end of 2009, or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the early part of their roll-out in August 2008 (the same timescale for market penetration had been stated by market intelligence company DRAMeXchange over a year earlier in April 2007. and by Desi Rhoden in 2005) The primary driving force behind the increased usage of DDR3 has been new Core i7 processors from Intel and Phenom II processors from AMD, both of which have internal memory controllers: the latter recommends DDR3, the former requires it. IDC stated in January 2009 that DDR3 sales will account for 29 percent of the total DRAM units sold in 2009, rising to 72% by 2011.

Successor

JEDEC's planned successor to DDR3 is DDR4, whose standard is currently in development. The primary benefits of DDR4 compared to DDR3 include a higher range of clock frequencies and data transfer rates and significantly lower voltage. Some manufacturers have already demonstrated DDR4 chips for testing purposes.

See also

Dual-channel architecture

Triple-channel architecture

List of device bandwidths

References

Category:SDRAM

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